new srd_logic type implementation for PDs to iterate over.

[libsigrokdecode.git] / decoders / uart.py

diff --git a/decoders/uart.py b/decoders/uart.py
index a089aa13195ca9cbc118247159ba1d74d93404d6..66deb5e2be7044edda76013ac2f6e9960ea94363 100644 (file)
--- a/decoders/uart.py
+++ b/decoders/uart.py
@@ -131,7 +131,7 @@ class Sample():
     def __init__(self, data):
         self.data = data
     def probe(self, probe):
-        s = ord(self.data[probe / 8]) & (1 << (probe % 8))
+        s = self.data[probe / 8] & (1 << (probe % 8))
         return True if s else False
 
 def sampleiter(data, unitsize):
@@ -194,6 +194,8 @@ class Decoder(sigrok.Decoder):
 
     def __init__(self, **kwargs):
         self.probes = Decoder.probes.copy()
+        self.output_protocol = None
+        self.output_annotation = None
 
         # Set defaults, can be overridden in 'start'.
         self.baudrate = 115200
@@ -227,6 +229,8 @@ class Decoder(sigrok.Decoder):
     def start(self, metadata):
         self.unitsize = metadata['unitsize']
         self.samplerate = metadata['samplerate']
+        # self.output_protocol = self.output_new(2)
+        self.output_annotation = self.output_new(1)
 
         # TODO
         ### self.baudrate = metadata['baudrate']
@@ -390,12 +394,10 @@ class Decoder(sigrok.Decoder):
              'data': None, 'ann': 'Stop bit'}]
         return o
 
-    def decode(self, data):
-        """UART protocol decoder"""
-
+    def decode(self, timeoffset, duration, data):
         out = []
 
-        for sample in sampleiter(data["data"], self.unitsize):
+        for sample in sampleiter(data, self.unitsize):
 
             # TODO: Eliminate the need for ord().
             s = ord(sample.data)
@@ -433,5 +435,6 @@ class Decoder(sigrok.Decoder):
             # self.oldtx = tx
 
         if out != []:
-            self.put(out)
+            # self.put(self.output_protocol, 0, 0, out_proto)
+            self.put(self.output_annotation, 0, 0, out)