+ return True
+
+ def handle_falling_edge_load(self):
+ if not self.handle_11bits():
+ return
+ s, v, g = self.dac_select, self.dac_value, self.gain
+ self.put(self.samplenum, self.samplenum, self.out_ann,
+ [3, ['Falling edge on LOAD', 'LOAD fall', 'F']])
+ if self.ldac == 0:
+ # If LDAC is low, the voltage is set immediately.
+ self.put(self.ss_dac, self.es_value, self.out_ann,
+ [7, ['Setting %s voltage to %d (x%d gain)' % (s, v, g),
+ '%s=%d (x%d gain)' % (s, v, g)]])
+ else:
+ # If LDAC is high, the voltage is not set immediately, but rather
+ # stored in a register. When LDAC goes low all four DAC voltages
+ # (DAC A/B/C/D) will be set at the same time.
+ self.put(self.ss_dac, self.es_value, self.out_ann,
+ [6, ['Setting %s register value to %d (x%d gain)' % \
+ (s, v, g), '%s=%d (x%d gain)' % (s, v, g)]])
+ # Save the last value the respective DAC was set to.
+ self.dacval[self.dac_select[-1]] = str(self.dac_value)
+
+ def handle_falling_edge_ldac(self):
+ self.put(self.samplenum, self.samplenum, self.out_ann,
+ [4, ['Falling edge on LDAC', 'LDAC fall', 'LDAC', 'L']])
+
+ # Don't emit any annotations if we didn't see any register writes.
+ if self.ss_dac_first is None:
+ return
+
+ s = ''.join(['DAC%s=%s ' % (d, self.dacval[d]) for d in 'ABCD']).strip()
+ self.put(self.ss_dac_first, self.samplenum, self.out_ann,
+ [8, ['Updating voltages: %s' % s, s, s.replace('DAC', '')]])
+ self.ss_dac_first = None
+
+ def handle_new_dac_bit(self):
+ self.bits.append([self.datapin, self.samplenum])
+