Various PDs: Minor consistency fixes.

[libsigrokdecode.git] / decoders / tlc5620 / pd.py

diff --git a/decoders/tlc5620/pd.py b/decoders/tlc5620/pd.py
index 6fedf5dc8037c20b203ed6d2077beb04d1618d3f..6e7c454df13d30c872eea856a54b9e58821e56d3 100644 (file)
--- a/decoders/tlc5620/pd.py
+++ b/decoders/tlc5620/pd.py
@@ -28,7 +28,7 @@ dacs = {
 }
 
 class Decoder(srd.Decoder):
-    api_version = 1
+    api_version = 2
     id = 'tlc5620'
     name = 'TI TLC5620'
     longname = 'Texas Instruments TLC5620'
@@ -36,11 +36,11 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['tlc5620']
-    probes = (
+    channels = (
         {'id': 'clk', 'name': 'CLK', 'desc': 'Serial interface clock'},
         {'id': 'data', 'name': 'DATA', 'desc': 'Serial interface data'},
     )
-    optional_probes = (
+    optional_channels = (
         {'id': 'load', 'name': 'LOAD', 'desc': 'Serial interface load control'},
         {'id': 'ldac', 'name': 'LDAC', 'desc': 'Load DAC'},
     )
@@ -62,11 +62,10 @@ class Decoder(srd.Decoder):
         self.dac_select = self.gain = self.dac_value = None
 
     def start(self):
-        # self.out_python = self.register(srd.OUTPUT_PYTHON)
         self.out_ann = self.register(srd.OUTPUT_ANN)
 
     def handle_11bits(self):
-        s = "".join(str(i) for i in self.bits[:2])
+        s = ''.join(str(i) for i in self.bits[:2])
         self.dac_select = s = dacs[int(s, 2)]
         self.put(self.ss_dac, self.es_dac, self.out_ann,
                  [0, ['DAC select: %s' % s, 'DAC sel: %s' % s,
@@ -76,7 +75,7 @@ class Decoder(srd.Decoder):
         self.put(self.ss_gain, self.es_gain, self.out_ann,
                  [1, ['Gain: x%d' % g, 'G: x%d' % g, 'x%d' % g]])
 
-        s = "".join(str(i) for i in self.bits[3:])
+        s = ''.join(str(i) for i in self.bits[3:])
         self.dac_value = v = int(s, 2)
         self.put(self.ss_value, self.es_value, self.out_ann,
                  [2, ['DAC value: %d' % v, 'Value: %d' % v, 'Val: %d' % v,