avr_isp: Add more parts

[libsigrokdecode.git] / decoders / tca6408a / pd.py

diff --git a/decoders/tca6408a/pd.py b/decoders/tca6408a/pd.py
index d53cf8ca7e793b9891cb2a28aed6eb4ae49c19b5..4ca1082a8bcfe9e2645d46ac502063332d898530 100644 (file)
--- a/decoders/tca6408a/pd.py
+++ b/decoders/tca6408a/pd.py
@@ -21,6 +21,14 @@
 
 import sigrokdecode as srd
 
+NUM_OUTPUT_CHANNELS = 8
+
+def logic_channels(num_channels):
+    l = []
+    for i in range(num_channels):
+        l.append(tuple(['p%d' % i, 'P-port input/output %d' % i]))
+    return tuple(l)
+
 class Decoder(srd.Decoder):
     api_version = 3
     id = 'tca6408a'
@@ -29,13 +37,14 @@ class Decoder(srd.Decoder):
     desc = 'Texas Instruments TCA6408A 8-bit I²C I/O expander.'
     license = 'gplv2+'
     inputs = ['i2c']
-    outputs = ['tca6408a']
+    outputs = []
     tags = ['Embedded/industrial', 'IC']
     annotations = (
         ('register', 'Register type'),
         ('value', 'Register value'),
-        ('warnings', 'Warning messages'),
+        ('warning', 'Warning'),
     )
+    logic_output_channels = logic_channels(NUM_OUTPUT_CHANNELS)
     annotation_rows = (
         ('regs', 'Registers', (0, 1)),
         ('warnings', 'Warnings', (2,)),
@@ -48,17 +57,33 @@ class Decoder(srd.Decoder):
         self.state = 'IDLE'
         self.chip = -1
 
+        self.logic_output_es = 0
+        self.logic_value = 0
+
     def start(self):
         self.out_ann = self.register(srd.OUTPUT_ANN)
+        self.out_logic = self.register(srd.OUTPUT_LOGIC)
+
+    def flush(self):
+        self.put_logic_states()
 
     def putx(self, data):
         self.put(self.ss, self.es, self.out_ann, data)
 
+    def put_logic_states(self):
+        if (self.es > self.logic_output_es):
+            data = bytes([self.logic_value])
+            self.put(self.logic_output_es, self.es, self.out_logic, [0, data])
+            self.logic_output_es = self.es
+
     def handle_reg_0x00(self, b):
         self.putx([1, ['State of inputs: %02X' % b]])
+        # TODO
 
     def handle_reg_0x01(self, b):
-        self.putx([1, ['Outputs set: %02X' % b ]])
+        self.put_logic_states()
+        self.putx([1, ['Outputs set: %02X' % b]])
+        self.logic_value = b
 
     def handle_reg_0x02(self, b):
         self.putx([1, ['Polarity inverted: %02X' % b]])