pca9571/tca6408a: Rework logic output

[libsigrokdecode.git] / decoders / tca6408a / pd.py

diff --git a/decoders/tca6408a/pd.py b/decoders/tca6408a/pd.py
index 49245174fc17e94f934c6161c547d1b4c08bdb3a..01c4e6d9bc764acd5db50458b1058d4b3b6236f3 100644 (file)
--- a/decoders/tca6408a/pd.py
+++ b/decoders/tca6408a/pd.py
@@ -21,6 +21,14 @@
 
 import sigrokdecode as srd
 
+NUM_OUTPUT_CHANNELS = 8
+
+def logic_channels(num_channels):
+    l = []
+    for i in range(num_channels):
+        l.append(tuple(['p%d' % i, 'P-port input/output %d' % i]))
+    return tuple(l)
+
 class Decoder(srd.Decoder):
     api_version = 3
     id = 'tca6408a'
@@ -34,8 +42,9 @@ class Decoder(srd.Decoder):
     annotations = (
         ('register', 'Register type'),
         ('value', 'Register value'),
-        ('warnings', 'Warning messages'),
+        ('warning', 'Warning'),
     )
+    logic_output_channels = logic_channels(NUM_OUTPUT_CHANNELS)
     annotation_rows = (
         ('regs', 'Registers', (0, 1)),
         ('warnings', 'Warnings', (2,)),
@@ -48,17 +57,33 @@ class Decoder(srd.Decoder):
         self.state = 'IDLE'
         self.chip = -1
 
+        self.logic_es = 1
+        self.logic_data = []
+        for i in range(NUM_OUTPUT_CHANNELS):
+            self.logic_data.append(bytes([1]))
+
     def start(self):
         self.out_ann = self.register(srd.OUTPUT_ANN)
+        self.out_logic = self.register(srd.OUTPUT_LOGIC)
 
     def putx(self, data):
         self.put(self.ss, self.es, self.out_ann, data)
 
+    def put_logic_states(self):
+        if (self.es > self.logic_es):
+            for i in range(NUM_OUTPUT_CHANNELS):
+                self.put(self.logic_es, self.es, self.out_logic, [i, self.logic_data[i]])
+            self.logic_es = self.es
+
     def handle_reg_0x00(self, b):
         self.putx([1, ['State of inputs: %02X' % b]])
+        # TODO
 
     def handle_reg_0x01(self, b):
-        self.putx([1, ['Outputs set: %02X' % b ]])
+        self.putx([1, ['Outputs set: %02X' % b]])
+        for i in range(NUM_OUTPUT_CHANNELS):
+            bit = (b & (1 << i)) != 0
+            self.logic_data[i] = bytes([bit])
 
     def handle_reg_0x02(self, b):
         self.putx([1, ['Polarity inverted: %02X' % b]])
@@ -88,6 +113,8 @@ class Decoder(srd.Decoder):
         # Store the start/end samples of this I²C packet.
         self.ss, self.es = ss, es
 
+        self.put_logic_states()
+
         # State machine.
         if self.state == 'IDLE':
             # Wait for an I²C START condition.