decoders: Add/update tags for each PD.

[libsigrokdecode.git] / decoders / st7735 / pd.py

diff --git a/decoders/st7735/pd.py b/decoders/st7735/pd.py
index f704c03a6f396840dec9bd042885d0e0aecdb23c..4ebb23d6e67840c56502f20105877e943b94c26c 100644 (file)
--- a/decoders/st7735/pd.py
+++ b/decoders/st7735/pd.py
@@ -73,6 +73,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['st7735']
+    tags = ['Display', 'IC']
     channels = (
         {'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'},
         {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'},
@@ -95,18 +96,15 @@ class Decoder(srd.Decoder):
         self.reset()
 
     def reset(self):
-        pass
-
-    def start(self):
-        self.out_ann = self.register(srd.OUTPUT_ANN)
-
-    def reset_state(self):
         self.accum_byte = 0
         self.accum_bits_num = 0
         self.bit_ss = -1
         self.byte_ss = -1
         self.current_bit = -1
 
+    def start(self):
+        self.out_ann = self.register(srd.OUTPUT_ANN)
+
     def put_desc(self, ss, es, cmd, data):
         if cmd == -1:
             return
@@ -130,13 +128,13 @@ class Decoder(srd.Decoder):
         current_data = []
         desc_ss = -1
         desc_es = -1
-        self.reset_state()
+        self.reset()
         while True:
             # Check data on both CLK edges.
             (cs, clk, mosi, dc) = self.wait({1: 'e'})
 
             if cs == 1: # Wait for CS = low, ignore the rest.
-                self.reset_state()
+                self.reset()
                 continue
 
             if clk == 1: