srd: Drop useless out_ann/out_proto init.

[libsigrokdecode.git] / decoders / srd_usb.py

diff --git a/decoders/srd_usb.py b/decoders/srd_usb.py
index 36fc9605712ba4b747a999f24455134e48f4b75e..c6e6627c3d4fbd47ee4becda5fd910185825894e 100644 (file)
--- a/decoders/srd_usb.py
+++ b/decoders/srd_usb.py
@@ -18,41 +18,37 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 

+#

 # USB Full-speed protocol decoder
 # USB Full-speed protocol decoder

-
-# Full-speed usb singalling consists of two signal lines, both driven at 3.3V
-# logic levels.  The signals are DP and DM, and normally operate in 
-# differential mode.  
+#
+# Full-speed USB signalling consists of two signal lines, both driven at 3.3V
+# logic levels. The signals are DP (D+) and DM (D-), and normally operate in
+# differential mode.

 # The state where DP=1,DM=0 is J, the state DP=0,DM=1 is K.
 # The state where DP=1,DM=0 is J, the state DP=0,DM=1 is K.

-# A state SE0 is defined where DP=DM=0.  This common mode signal is used to
+# A state SE0 is defined where DP=DM=0. This common mode signal is used to

 # signal a reset or end of packet.
 # signal a reset or end of packet.

-
-# Data transmitted on the USB is encoded with NRZI.  A transision from J to K
-# or vice-versa indicates a logic 0, while no transision indicates a logic 1.
-# If 6 ones are transmitted consecutively, a zero is inserted to force a 
-# transition.  This is known as bit stuffing.  Data is transferred at a rate 
-# of 12Mbit/s.  The SE0 transmitted to signal an end-of-packet is two bit 
+#
+# Data transmitted on the USB is encoded with NRZI. A transition from J to K
+# or vice-versa indicates a logic 0, while no transition indicates a logic 1.
+# If 6 ones are transmitted consecutively, a zero is inserted to force a
+# transition. This is known as bit stuffing. Data is transferred at a rate
+# of 12Mbit/s. The SE0 transmitted to signal an end-of-packet is two bit

 # intervals long.
 # intervals long.

+#
+# Details:
+# https://en.wikipedia.org/wiki/USB
+# http://www.usb.org/developers/docs/
+#

 
 

-import sigrok
-
-class Sample():
-    def __init__(self, data):
-        self.data = data
-    def probe(self, probe):
-        s = ord(self.data[probe / 8]) & (1 << (probe % 8))
-        return True if s else False
-
-def sampleiter(data, unitsize):
-    for i in range(0, len(data), unitsize):
-        yield(Sample(data[i:i+unitsize]))
+import sigrokdecode as srd

 
 

+# States

 SE0, J, K, SE1 = 0, 1, 2, 3
 syms = {
 SE0, J, K, SE1 = 0, 1, 2, 3
 syms = {

-        (False, False): SE0,
-        (True, False): J,
-        (False, True): K,
-        (True, True): SE1,
+        (0, 0): SE0,
+        (1, 0): J,
+        (0, 1): K,
+        (1, 1): SE1,

 }
 
 def bitstr_to_num(bitstr):
 }
 
 def bitstr_to_num(bitstr):


@@ -62,13 +58,14 @@ def bitstr_to_num(bitstr):
     return int(''.join(l), 2)
 
 def packet_decode(packet):
     return int(''.join(l), 2)
 
 def packet_decode(packet):

-    pids = {'10000111':'OUT',  #Tokens
+    pids = {
+        '10000111':'OUT',      # Tokens

         '10010110':'IN',
         '10100101':'SOF',
         '10110100':'SETUP',
         '10010110':'IN',
         '10100101':'SOF',
         '10110100':'SETUP',

-        '11000011':'DATA0',    #Data
+        '11000011':'DATA0',    # Data

         '11010010':'DATA1',
         '11010010':'DATA1',

-        '01001011':'ACK',      #Handshake
+        '01001011':'ACK',      # Handshake

         '01011010':'NAK',
         '01111000':'STALL',
         '01101001':'NYET',
         '01011010':'NAK',
         '01111000':'STALL',
         '01101001':'NYET',


@@ -77,7 +74,7 @@ def packet_decode(packet):
     sync = packet[:8]
     pid = packet[8:16]
     pid = pids.get(pid, pid)
     sync = packet[:8]
     pid = packet[8:16]
     pid = pids.get(pid, pid)

-    #Remove CRC
+    # Remove CRC.

     if pid in ('OUT', 'IN', 'SOF', 'SETUP'):
         data = packet[16:-5]
         if pid == 'SOF':
     if pid in ('OUT', 'IN', 'SOF', 'SETUP'):
         data = packet[16:-5]
         if pid == 'SOF':


@@ -99,10 +96,11 @@ def packet_decode(packet):
 
     if sync != "00000001":
         return "SYNC INVALID!"
 
     if sync != "00000001":
         return "SYNC INVALID!"

-    
+

     return pid + ' ' + data
 
     return pid + ' ' + data
 

-class Decoder():
+class Decoder(srd.Decoder):
+    id = 'usb'

     name = 'USB'
     desc = 'Universal Serial Bus'
     longname = '...longname...'
     name = 'USB'
     desc = 'Universal Serial Bus'
     longname = '...longname...'


@@ -113,53 +111,59 @@ class Decoder():
     inputs = ['logic']
     outputs = ['usb']
     # Probe names with a set of defaults
     inputs = ['logic']
     outputs = ['usb']
     # Probe names with a set of defaults

-    probes = {'dp':0, 'dm':1}
+    probes = [
+        {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
+        {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
+    ]

     options = {}
 
     def __init__(self):
     options = {}
 
     def __init__(self):

-        self.probes = Decoder.probes.copy()
+        pass

 
     def start(self, metadata):
 
     def start(self, metadata):

-        self.unitsize = metadata['unitsize']

         self.rate = metadata['samplerate']
         self.rate = metadata['samplerate']

+        # self.out_proto = self.add(srd.SRD_OUTPUT_PROTO, 'usb')
+        self.out_ann = self.add(srd.SRD_OUTPUT_ANN, 'usb')

         if self.rate < 48000000:
             raise Exception("Sample rate not sufficient for USB decoding")
         if self.rate < 48000000:
             raise Exception("Sample rate not sufficient for USB decoding")

-        # initialise decoder state
+        # Initialise decoder state.

         self.sym = J
         self.scount = 0
         self.packet = ''
 
         self.sym = J
         self.scount = 0
         self.packet = ''
 

-    def decode(self, data):
-        for sample in sampleiter(data['data'], self.unitsize):
+    def decode(self, timeoffset, duration, data):
+        out = []
+
+        # FIXME
+        for (samplenum, (dp, dm, x, y, z, a)) in data:

 
             self.scount += 1
 
 
             self.scount += 1
 

-            sym = syms[sample.probe(self.probes['dp']), 
-                        sample.probe(self.probes['dm'])] 
+            sym = syms[dp, dm]

             if sym == self.sym:
                 continue
 
             if self.scount == 1:
             if sym == self.sym:
                 continue
 
             if self.scount == 1:

-                # We ignore single sample width pulses. 
-                # I sometimes get these with the OLS
+                # We ignore single sample width pulses.
+                # I sometimes get these with the OLS.

                 self.sym = sym
                 self.scount = 0
                 continue
 
                 self.sym = sym
                 self.scount = 0
                 continue
 

-            # how many bits since the last transition?
+            # How many bits since the last transition?

             if self.packet or self.sym != J:
             if self.packet or self.sym != J:

-                bitcount = (self.scount - 1) * 12000000 / self.rate
+                bitcount = int((self.scount - 1) * 12000000 / self.rate)

             else:
                 bitcount = 0
 
             if self.sym == SE0:
                 if bitcount == 1:
             else:
                 bitcount = 0
 
             if self.sym == SE0:
                 if bitcount == 1:

-                    # End-Of-Packet
-                    sigrok.put({"type":"usb", "data":self.packet, 
-                                "display":packet_decode(self.packet)})
+                    # End-Of-Packet (EOP)
+                    out += [{"type":"usb", "data":self.packet,
+                              "display":packet_decode(self.packet)}]

                 else:
                 else:

-                     # Longer than EOP, assume reset
-                    sigrok.put({"type":"usb", "display":"RESET"})
+                    # Longer than EOP, assume reset.
+                    out += [{"type":"usb", "display":"RESET"}]

                 self.scount = 0
                 self.sym = sym
                 self.packet = ''
                 self.scount = 0
                 self.sym = sym
                 self.packet = ''


@@ -167,12 +171,16 @@ class Decoder():
 
             # Add bits to the packet string.
             self.packet += '1' * bitcount
 
             # Add bits to the packet string.
             self.packet += '1' * bitcount

-            # Handle bit stuffing
+            # Handle bit stuffing.

             if bitcount < 6 and sym != SE0:
                 self.packet += '0'
             elif bitcount > 6:
             if bitcount < 6 and sym != SE0:
                 self.packet += '0'
             elif bitcount > 6:

-                sigrok.put({"type":"usb", "display":"BIT STUFF ERROR"})
-            
+                out += [{"type":"usb", "display":"BIT STUFF ERROR"}]
+

             self.scount = 0
             self.sym = sym
 
             self.scount = 0
             self.sym = sym
 

+        if out != []:
+            # self.put(0, 0, self.out_proto, out_proto)
+            self.put(0, 0, self.out_ann, out)
+