new srd_logic type implementation for PDs to iterate over.

[libsigrokdecode.git] / decoders / srd_usb.py

diff --git a/decoders/srd_usb.py b/decoders/srd_usb.py
index a223dbbade809f642355e4f60eed264769d8ed7e..2db0158640406aeb5073f7c86d041d3602e7e6ee 100644 (file)
--- a/decoders/srd_usb.py
+++ b/decoders/srd_usb.py
@@ -46,7 +46,7 @@ class Sample():
     def __init__(self, data):
         self.data = data
     def probe(self, probe):
-        s = ord(self.data[int(probe / 8)]) & (1 << (probe % 8))
+        s = self.data[int(probe / 8)] & (1 << (probe % 8))
         return True if s else False
 
 def sampleiter(data, unitsize):