srd: rename extra_probes to optional_probes in all PDs

[libsigrokdecode.git] / decoders / spi / spi.py

diff --git a/decoders/spi/spi.py b/decoders/spi/spi.py
index 57f55624ffe4c5ed5d27de921c6ada1d6ffc74d0..ff186ddcf56d6280101c671317ee8173a8cf404c 100644 (file)
--- a/decoders/spi/spi.py
+++ b/decoders/spi/spi.py
@@ -59,13 +59,14 @@ class Decoder(srd.Decoder):
     inputs = ['logic']
     outputs = ['spi']
     probes = [
-        {'id': 'mosi', 'name': 'MOSI',
-         'desc': 'SPI MOSI line (Master out, slave in)'},
         {'id': 'miso', 'name': 'MISO',
          'desc': 'SPI MISO line (Master in, slave out)'},
+        {'id': 'mosi', 'name': 'MOSI',
+         'desc': 'SPI MOSI line (Master out, slave in)'},
         {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
         {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
     ]
+    optional_probes = [] # TODO
     options = {
         'cs_polarity': ['CS# polarity', ACTIVE_LOW],
         'cpol': ['Clock polarity', CPOL_0],
@@ -94,11 +95,8 @@ class Decoder(srd.Decoder):
         return 'SPI: %d bytes received' % self.bytesreceived
 
     def decode(self, ss, es, data):
-        # HACK! At the moment the number of probes is not handled correctly.
-        # E.g. if an input file (-i foo.sr) has more than two probes enabled.
-        # for (samplenum, (mosi, sck, x, y, z, a)) in data:
-        # for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
-        for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
+        # TODO: Either MISO or MOSI could be optional. CS# is optional.
+        for (samplenum, (miso, mosi, sck, cs)) in data:
 
             self.samplenum += 1 # FIXME
 
@@ -127,22 +125,24 @@ class Decoder(srd.Decoder):
                 if deasserted:
                     self.cs_was_deasserted_during_data_word = 1
 
+            ws = self.options['wordsize']
+
             # Receive MOSI bit into our shift register.
             if self.options['bitorder'] == MSB_FIRST:
-                self.mosidata |= mosi << (self.options['wordsize'] - 1 - self.bitcount)
+                self.mosidata |= mosi << (ws - 1 - self.bitcount)
             else:
                 self.mosidata |= mosi << self.bitcount
 
             # Receive MISO bit into our shift register.
             if self.options['bitorder'] == MSB_FIRST:
-                self.misodata |= miso << (self.options['wordsize'] - 1 - self.bitcount)
+                self.misodata |= miso << (ws - 1 - self.bitcount)
             else:
                 self.misodata |= miso << self.bitcount
 
             self.bitcount += 1
 
-            # Continue to receive if not a byte yet.
-            if self.bitcount != self.options['wordsize']:
+            # Continue to receive if not enough bits were received, yet.
+            if self.bitcount != ws:
                 continue
 
             self.put(self.start_sample, self.samplenum, self.out_proto,