srd: Decoders: Fix/simplify samplenum usage.

[libsigrokdecode.git] / decoders / spi / spi.py

diff --git a/decoders/spi/spi.py b/decoders/spi/spi.py
index dfe83b95499f16587d1c4672546c8a0e752307b7..5e5e74ec5c7123d8a022beb0086e04a7e1f17dc8 100644 (file)
--- a/decoders/spi/spi.py
+++ b/decoders/spi/spi.py
@@ -42,7 +42,6 @@ class Decoder(srd.Decoder):
     name = 'SPI'
     longname = 'Serial Peripheral Interface'
     desc = '...desc...'
-    longdesc = '...longdesc...'
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['spi']
@@ -84,9 +83,7 @@ class Decoder(srd.Decoder):
 
     def decode(self, ss, es, data):
         # TODO: Either MISO or MOSI could be optional. CS# is optional.
-        for (samplenum, (miso, mosi, sck, cs)) in data:
-
-            self.samplenum += 1 # FIXME
+        for (self.samplenum, (miso, mosi, sck, cs)) in data:
 
             # Ignore sample if the clock pin hasn't changed.
             if sck == self.oldsck:
@@ -107,7 +104,7 @@ class Decoder(srd.Decoder):
 
             # If this is the first bit, save its sample number.
             if self.bitcount == 0:
-                self.start_sample = samplenum
+                self.start_sample = self.samplenum
                 active_low = (self.options['cs_polarity'] == 'active-low')
                 deasserted = cs if active_low else not cs
                 if deasserted: