srd: Performance improvements for various PDs.

[libsigrokdecode.git] / decoders / spi / spi.py

diff --git a/decoders/spi/spi.py b/decoders/spi/spi.py
index ff186ddcf56d6280101c671317ee8173a8cf404c..10857866f4cad8ebdc41fe58600cdb688b8d6420 100644 (file)
--- a/decoders/spi/spi.py
+++ b/decoders/spi/spi.py
@@ -19,25 +19,13 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-import sigrokdecode as srd
-
-# Chip-select options
-ACTIVE_LOW = 0
-ACTIVE_HIGH = 1
-
-# Clock polarity options
-CPOL_0 = 0 # Clock is low when inactive
-CPOL_1 = 1 # Clock is high when inactive
-
-# Clock phase options
-CPHA_0 = 0 # Data is valid on the leading clock edge
-CPHA_1 = 1 # Data is valid on the trailing clock edge
+# SPI protocol decoder
 
-# Bit order options
-MSB_FIRST = 0
-LSB_FIRST = 1
+import sigrokdecode as srd
 
 # Key: (CPOL, CPHA). Value: SPI mode.
+# Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
+# Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
 spi_mode = {
     (0, 0): 0, # Mode 0
     (0, 1): 1, # Mode 1
@@ -53,8 +41,7 @@ class Decoder(srd.Decoder):
     id = 'spi'
     name = 'SPI'
     longname = 'Serial Peripheral Interface'
-    desc = '...desc...'
-    longdesc = '...longdesc...'
+    desc = 'Full-duplex, synchronous, serial bus.'
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['spi']
@@ -68,10 +55,10 @@ class Decoder(srd.Decoder):
     ]
     optional_probes = [] # TODO
     options = {
-        'cs_polarity': ['CS# polarity', ACTIVE_LOW],
-        'cpol': ['Clock polarity', CPOL_0],
-        'cpha': ['Clock phase', CPHA_0],
-        'bitorder': ['Bit order within the SPI data', MSB_FIRST],
+        'cs_polarity': ['CS# polarity', 'active-low'],
+        'cpol': ['Clock polarity', 0],
+        'cpha': ['Clock phase', 0],
+        'bitorder': ['Bit order within the SPI data', 'msb-first'],
         'wordsize': ['Word size of SPI data', 8], # 1-64?
     }
     annotations = [
@@ -86,6 +73,8 @@ class Decoder(srd.Decoder):
         self.bytesreceived = 0
         self.samplenum = -1
         self.cs_was_deasserted_during_data_word = 0
+        self.oldcs = -1
+        self.oldpins = None
 
     def start(self, metadata):
         self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
@@ -96,9 +85,20 @@ class Decoder(srd.Decoder):
 
     def decode(self, ss, es, data):
         # TODO: Either MISO or MOSI could be optional. CS# is optional.
-        for (samplenum, (miso, mosi, sck, cs)) in data:
+        for (self.samplenum, pins) in data:
+
+            # Ignore identical samples early on (for performance reasons).
+            if self.oldpins == pins:
+                continue
+            self.oldpins, (miso, mosi, sck, cs) = pins, pins
 
-            self.samplenum += 1 # FIXME
+            if self.oldcs != cs:
+                # Send all CS# pin value changes.
+                self.put(self.samplenum, self.samplenum, self.out_proto,
+                         ['CS-CHANGE', self.oldcs, cs])
+                self.put(self.samplenum, self.samplenum, self.out_ann,
+                         [0, ['CS-CHANGE: %d->%d' % (self.oldcs, cs)]])
+                self.oldcs = cs
 
             # Ignore sample if the clock pin hasn't changed.
             if sck == self.oldsck:
@@ -119,8 +119,8 @@ class Decoder(srd.Decoder):
 
             # If this is the first bit, save its sample number.
             if self.bitcount == 0:
-                self.start_sample = samplenum
-                active_low = (self.options['cs_polarity'] == ACTIVE_LOW)
+                self.start_sample = self.samplenum
+                active_low = (self.options['cs_polarity'] == 'active-low')
                 deasserted = cs if active_low else not cs
                 if deasserted:
                     self.cs_was_deasserted_during_data_word = 1
@@ -128,13 +128,13 @@ class Decoder(srd.Decoder):
             ws = self.options['wordsize']
 
             # Receive MOSI bit into our shift register.
-            if self.options['bitorder'] == MSB_FIRST:
+            if self.options['bitorder'] == 'msb-first':
                 self.mosidata |= mosi << (ws - 1 - self.bitcount)
             else:
                 self.mosidata |= mosi << self.bitcount
 
             # Receive MISO bit into our shift register.
-            if self.options['bitorder'] == MSB_FIRST:
+            if self.options['bitorder'] == 'msb-first':
                 self.misodata |= miso << (ws - 1 - self.bitcount)
             else:
                 self.misodata |= miso << self.bitcount
@@ -146,7 +146,7 @@ class Decoder(srd.Decoder):
                 continue
 
             self.put(self.start_sample, self.samplenum, self.out_proto,
-                     ['data', self.mosidata, self.misodata])
+                     ['DATA', self.mosidata, self.misodata])
             self.put(self.start_sample, self.samplenum, self.out_ann,
                      [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata,
                      self.misodata)]])