srd: Performance improvements for various PDs.

[libsigrokdecode.git] / decoders / spi / spi.py

diff --git a/decoders/spi/spi.py b/decoders/spi/spi.py
index bbf0f3705af62f9762794d3e19cf064ccd84f793..10857866f4cad8ebdc41fe58600cdb688b8d6420 100644 (file)
--- a/decoders/spi/spi.py
+++ b/decoders/spi/spi.py
@@ -19,6 +19,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
+# SPI protocol decoder
+
 import sigrokdecode as srd
 
 # Key: (CPOL, CPHA). Value: SPI mode.
@@ -39,8 +41,7 @@ class Decoder(srd.Decoder):
     id = 'spi'
     name = 'SPI'
     longname = 'Serial Peripheral Interface'
-    desc = '...desc...'
-    longdesc = '...longdesc...'
+    desc = 'Full-duplex, synchronous, serial bus.'
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['spi']
@@ -72,6 +73,8 @@ class Decoder(srd.Decoder):
         self.bytesreceived = 0
         self.samplenum = -1
         self.cs_was_deasserted_during_data_word = 0
+        self.oldcs = -1
+        self.oldpins = None
 
     def start(self, metadata):
         self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
@@ -82,9 +85,20 @@ class Decoder(srd.Decoder):
 
     def decode(self, ss, es, data):
         # TODO: Either MISO or MOSI could be optional. CS# is optional.
-        for (samplenum, (miso, mosi, sck, cs)) in data:
+        for (self.samplenum, pins) in data:
+
+            # Ignore identical samples early on (for performance reasons).
+            if self.oldpins == pins:
+                continue
+            self.oldpins, (miso, mosi, sck, cs) = pins, pins
 
-            self.samplenum += 1 # FIXME
+            if self.oldcs != cs:
+                # Send all CS# pin value changes.
+                self.put(self.samplenum, self.samplenum, self.out_proto,
+                         ['CS-CHANGE', self.oldcs, cs])
+                self.put(self.samplenum, self.samplenum, self.out_ann,
+                         [0, ['CS-CHANGE: %d->%d' % (self.oldcs, cs)]])
+                self.oldcs = cs
 
             # Ignore sample if the clock pin hasn't changed.
             if sck == self.oldsck:
@@ -105,7 +119,7 @@ class Decoder(srd.Decoder):
 
             # If this is the first bit, save its sample number.
             if self.bitcount == 0:
-                self.start_sample = samplenum
+                self.start_sample = self.samplenum
                 active_low = (self.options['cs_polarity'] == 'active-low')
                 deasserted = cs if active_low else not cs
                 if deasserted:
@@ -132,7 +146,7 @@ class Decoder(srd.Decoder):
                 continue
 
             self.put(self.start_sample, self.samplenum, self.out_proto,
-                     ['data', self.mosidata, self.misodata])
+                     ['DATA', self.mosidata, self.misodata])
             self.put(self.start_sample, self.samplenum, self.out_ann,
                      [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata,
                      self.misodata)]])