(1, 1): 3, # Mode 3
}
-class SamplerateError(Exception):
- pass
-
class ChannelError(Exception):
pass
license = 'gplv2+'
inputs = ['logic']
outputs = ['spi']
+ tags = ['Embedded/industrial']
channels = (
{'id': 'clk', 'name': 'CLK', 'desc': 'Clock'},
)
annotations = (
('miso-data', 'MISO data'),
('mosi-data', 'MOSI data'),
- ('miso-bits', 'MISO bits'),
- ('mosi-bits', 'MOSI bits'),
- ('warnings', 'Human-readable warnings'),
+ ('miso-bit', 'MISO bit'),
+ ('mosi-bit', 'MOSI bit'),
+ ('warning', 'Warning'),
+ ('miso-transfer', 'MISO transfer'),
+ ('mosi-transfer', 'MOSI transfer'),
)
annotation_rows = (
- ('miso-data', 'MISO data', (0,)),
('miso-bits', 'MISO bits', (2,)),
- ('mosi-data', 'MOSI data', (1,)),
+ ('miso-data-vals', 'MISO data', (0,)),
+ ('miso-transfers', 'MISO transfers', (5,)),
('mosi-bits', 'MOSI bits', (3,)),
+ ('mosi-data-vals', 'MOSI data', (1,)),
+ ('mosi-transfers', 'MOSI transfers', (6,)),
('other', 'Other', (4,)),
)
binary = (
)
def __init__(self):
+ self.reset()
+
+ def reset(self):
self.samplerate = None
- self.oldclk = 1
self.bitcount = 0
self.misodata = self.mosidata = 0
self.misobits = []
self.misobytes = []
self.mosibytes = []
self.ss_block = -1
- self.samplenum = -1
self.ss_transfer = -1
self.cs_was_deasserted = False
- self.oldcs = None
self.have_cs = self.have_miso = self.have_mosi = None
- def metadata(self, key, value):
- if key == srd.SRD_CONF_SAMPLERATE:
- self.samplerate = value
-
def start(self):
self.out_python = self.register(srd.OUTPUT_PYTHON)
self.out_ann = self.register(srd.OUTPUT_ANN)
meta=(int, 'Bitrate', 'Bitrate during transfers'))
self.bw = (self.options['wordsize'] + 7) // 8
+ def metadata(self, key, value):
+ if key == srd.SRD_CONF_SAMPLERATE:
+ self.samplerate = value
+
def putw(self, data):
self.put(self.ss_block, self.samplenum, self.out_ann, data)
not self.cs_asserted(cs) if self.have_cs else False
ws = self.options['wordsize']
+ bo = self.options['bitorder']
# Receive MISO bit into our shift register.
if self.have_miso:
- if self.options['bitorder'] == 'msb-first':
+ if bo == 'msb-first':
self.misodata |= miso << (ws - 1 - self.bitcount)
else:
self.misodata |= miso << self.bitcount
# Receive MOSI bit into our shift register.
if self.have_mosi:
- if self.options['bitorder'] == 'msb-first':
+ if bo == 'msb-first':
self.mosidata |= mosi << (ws - 1 - self.bitcount)
else:
self.mosidata |= mosi << self.bitcount
self.putdata()
# Meta bitrate.
- elapsed = 1 / float(self.samplerate)
- elapsed *= (self.samplenum - self.ss_block + 1)
- bitrate = int(1 / elapsed * self.options['wordsize'])
- self.put(self.ss_block, self.samplenum, self.out_bitrate, bitrate)
+ if self.samplerate:
+ elapsed = 1 / float(self.samplerate)
+ elapsed *= (self.samplenum - self.ss_block + 1)
+ bitrate = int(1 / elapsed * ws)
+ self.put(self.ss_block, self.samplenum, self.out_bitrate, bitrate)
if self.have_cs and self.cs_was_deasserted:
self.putw([4, ['CS# was deasserted during this data word!']])
self.reset_decoder_state()
- def find_clk_edge(self, miso, mosi, clk, cs):
- if self.have_cs and self.oldcs != cs:
+ def find_clk_edge(self, miso, mosi, clk, cs, first):
+ if self.have_cs and (first or self.matched[self.have_cs]):
# Send all CS# pin value changes.
+ oldcs = None if first else 1 - cs
self.put(self.samplenum, self.samplenum, self.out_python,
- ['CS-CHANGE', self.oldcs, cs])
- self.oldcs = cs
+ ['CS-CHANGE', oldcs, cs])
if self.cs_asserted(cs):
self.ss_transfer = self.samplenum
self.misobytes = []
self.mosibytes = []
- else:
+ elif self.ss_transfer != -1:
+ if self.have_miso:
+ self.put(self.ss_transfer, self.samplenum, self.out_ann,
+ [5, [' '.join(format(x.val, '02X') for x in self.misobytes)]])
+ if self.have_mosi:
+ self.put(self.ss_transfer, self.samplenum, self.out_ann,
+ [6, [' '.join(format(x.val, '02X') for x in self.mosibytes)]])
self.put(self.ss_transfer, self.samplenum, self.out_python,
['TRANSFER', self.mosibytes, self.misobytes])
return
# Ignore sample if the clock pin hasn't changed.
- if clk == self.oldclk:
+ if first or not self.matched[0]:
return
- self.oldclk = clk
-
# Sample data on rising/falling clock edge (depends on mode).
mode = spi_mode[self.options['cpol'], self.options['cpha']]
if mode == 0 and clk == 0: # Sample on rising clock edge
self.handle_bit(miso, mosi, clk, cs)
def decode(self):
- if not self.samplerate:
- raise SamplerateError('Cannot decode without samplerate.')
-
- # Either MISO or MOSI can be omitted (but not both). CS# is optional.
+ # The CLK input is mandatory. Other signals are (individually)
+ # optional. Yet either MISO or MOSI (or both) must be provided.
+ # Tell stacked decoders when we don't have a CS# signal.
+ if not self.has_channel(0):
+ raise ChannelError('Either MISO or MOSI (or both) pins required.')
self.have_miso = self.has_channel(1)
self.have_mosi = self.has_channel(2)
- self.have_cs = self.has_channel(3)
if not self.have_miso and not self.have_mosi:
raise ChannelError('Either MISO or MOSI (or both) pins required.')
-
- # Tell stacked decoders that we don't have a CS# signal.
+ self.have_cs = self.has_channel(3)
if not self.have_cs:
self.put(0, 0, self.out_python, ['CS-CHANGE', None, None])
+ # We want all CLK changes. We want all CS changes if CS is used.
+ # Map 'have_cs' from boolean to an integer index. This simplifies
+ # evaluation in other locations.
+ wait_cond = [{0: 'e'}]
+ if self.have_cs:
+ self.have_cs = len(wait_cond)
+ wait_cond.append({3: 'e'})
+
# "Pixel compatibility" with the v2 implementation. Grab and
# process the very first sample before checking for edges. The
- # previous implementation did this by seeding old values with None,
- # which led to an immediate "change" in comparison.
- pins = self.wait({})
- (clk, miso, mosi, cs) = pins
- self.find_clk_edge(miso, mosi, clk, cs)
+ # previous implementation did this by seeding old values with
+ # None, which led to an immediate "change" in comparison.
+ (clk, miso, mosi, cs) = self.wait({})
+ self.find_clk_edge(miso, mosi, clk, cs, True)
while True:
- # Ignore identical samples early on (for performance reasons).
- pins = self.wait([{0: 'e'}, {1: 'e'}, {2: 'e'}, {3: 'e'}])
- (clk, miso, mosi, cs) = pins
- self.find_clk_edge(miso, mosi, clk, cs)
+ (clk, miso, mosi, cs) = self.wait(wait_cond)
+ self.find_clk_edge(miso, mosi, clk, cs, False)
projects / libsigrokdecode.git / blobdiff