spi: Improve probe names/descriptions a bit.

[libsigrokdecode.git] / decoders / spi / pd.py

diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py
index a7830cdde2a4d0e3f0b0bebc0a7add3f8d7240c1..e6e45c46d179c5b290b5cdf0b3c0e163fab5a64a 100644 (file)
--- a/decoders/spi/pd.py
+++ b/decoders/spi/pd.py
@@ -22,7 +22,7 @@
 import sigrokdecode as srd
 
 '''
-Protocol output format:
+OUTPUT_PYTHON format:
 
 SPI packet:
 [<cmd>, <data1>, <data2>]
@@ -64,14 +64,12 @@ class Decoder(srd.Decoder):
     inputs = ['logic']
     outputs = ['spi']
     probes = [
-        {'id': 'clk', 'name': 'CLK', 'desc': 'SPI clock line'},
+        {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'},
     ]
     optional_probes = [
-        {'id': 'miso', 'name': 'MISO',
-         'desc': 'SPI MISO line (master in, slave out)'},
-        {'id': 'mosi', 'name': 'MOSI',
-         'desc': 'SPI MOSI line (master out, slave in)'},
-        {'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'},
+        {'id': 'miso', 'name': 'MISO', 'desc': 'Master in, slave out'},
+        {'id': 'mosi', 'name': 'MOSI', 'desc': 'Master out, slave in'},
+        {'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'},
     ]
     options = {
         'cs_polarity': ['CS# polarity', 'active-low'],
@@ -86,6 +84,11 @@ class Decoder(srd.Decoder):
         ['mosi-data', 'MOSI SPI data'],
         ['warnings', 'Human-readable warnings'],
     ]
+    annotation_rows = (
+        ('miso', 'MISO', (0,)),
+        ('mosi', 'MOSI', (1,)),
+        ('other', 'Other', (2,)),
+    )
 
     def __init__(self):
         self.samplerate = None
@@ -108,13 +111,13 @@ class Decoder(srd.Decoder):
             self.samplerate = value
 
     def start(self):
-        self.out_proto = self.register(srd.OUTPUT_PYTHON)
+        self.out_python = self.register(srd.OUTPUT_PYTHON)
         self.out_ann = self.register(srd.OUTPUT_ANN)
         self.out_bitrate = self.register(srd.OUTPUT_META,
                 meta=(int, 'Bitrate', 'Bitrate during transfers'))
 
     def putpw(self, data):
-        self.put(self.startsample, self.samplenum, self.out_proto, data)
+        self.put(self.startsample, self.samplenum, self.out_python, data)
 
     def putw(self, data):
         self.put(self.startsample, self.samplenum, self.out_ann, data)
@@ -179,7 +182,7 @@ class Decoder(srd.Decoder):
     def find_clk_edge(self, miso, mosi, clk, cs):
         if self.have_cs and self.oldcs != cs:
             # Send all CS# pin value changes.
-            self.put(self.samplenum, self.samplenum, self.out_proto,
+            self.put(self.samplenum, self.samplenum, self.out_python,
                      ['CS-CHANGE', self.oldcs, cs])
             self.oldcs = cs
             # Reset decoder state when CS# changes (and the CS# pin is used).