import sigrokdecode as srd
+'''
+Protocol output format:
+
+SPI packet:
+[<cmd>, <data1>, <data2>]
+
+Commands:
+ - 'DATA': <data1> contains the MISO data, <data2> contains the MOSI data.
+ The data is _usually_ 8 bits (but can also be fewer or more bits).
+ Both data items are Python numbers, not strings.
+ - 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
+ Both data items are Python numbers (0/1), not strings.
+
+Examples:
+ ['CS-CHANGE', 1, 0]
+ ['DATA', 0xff, 0x3a]
+ ['DATA', 0x65, 0x00]
+ ['CS-CHANGE', 0, 1]
+'''
+
# Key: (CPOL, CPHA). Value: SPI mode.
# Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
# Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
{'id': 'mosi', 'name': 'MOSI',
'desc': 'SPI MOSI line (Master out, slave in)'},
{'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
- {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
]
- optional_probes = [] # TODO
+ optional_probes = [
+ {'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'},
+ ]
options = {
'cs_polarity': ['CS# polarity', 'active-low'],
'cpol': ['Clock polarity', 0],
]
def __init__(self):
+ self.samplerate = None
self.oldsck = 1
self.bitcount = 0
self.mosidata = 0
self.misodata = 0
- self.bytesreceived = 0
self.startsample = -1
self.samplenum = -1
self.cs_was_deasserted_during_data_word = 0
self.oldpins = None
self.state = 'IDLE'
- def start(self, metadata):
- self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
- self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
+ def metadata(self, key, value):
+ if key == srd.SRD_CONF_SAMPLERATE:
+ self.samplerate = value
- def report(self):
- return 'SPI: %d bytes received' % self.bytesreceived
+ def start(self):
+ self.out_proto = self.register(srd.OUTPUT_PYTHON)
+ self.out_ann = self.register(srd.OUTPUT_ANN)
+ self.out_bitrate = self.register(srd.OUTPUT_META,
+ meta=(int, 'Bitrate', 'Bitrate during transfers'))
def putpw(self, data):
self.put(self.startsample, self.samplenum, self.out_proto, data)
# If this is the first bit, save its sample number.
if self.bitcount == 0:
self.startsample = self.samplenum
- active_low = (self.options['cs_polarity'] == 'active-low')
- deasserted = cs if active_low else not cs
- if deasserted:
- self.cs_was_deasserted_during_data_word = 1
+ if self.have_cs:
+ active_low = (self.options['cs_polarity'] == 'active-low')
+ deasserted = cs if active_low else not cs
+ if deasserted:
+ self.cs_was_deasserted_during_data_word = 1
ws = self.options['wordsize']
if self.bitcount != ws:
return
+ # Pass MOSI and MISO to the next PD up the stack
self.putpw(['DATA', self.mosidata, self.misodata])
+
+ # Annotations
self.putw([0, ['%02X/%02X' % (self.mosidata, self.misodata)]])
self.putw([1, ['%02X' % self.misodata]])
self.putw([2, ['%02X' % self.mosidata]])
+ # Meta bitrate
+ elapsed = 1 / float(self.samplerate) * (self.samplenum - self.startsample + 1)
+ bitrate = int(1 / elapsed * self.options['wordsize'])
+ self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate)
+
if self.cs_was_deasserted_during_data_word:
self.putw([3, ['CS# was deasserted during this data word!']])
# Reset decoder state.
- self.mosidata = 0
- self.misodata = 0
- self.bitcount = 0
-
- # Keep stats for summary.
- self.bytesreceived += 1
+ self.mosidata = self.misodata = self.bitcount = 0
def find_clk_edge(self, miso, mosi, sck, cs):
- if self.oldcs != cs:
+ if self.have_cs and self.oldcs != cs:
# Send all CS# pin value changes.
self.put(self.samplenum, self.samplenum, self.out_proto,
['CS-CHANGE', self.oldcs, cs])
self.oldcs = cs
+ # Reset decoder state when CS# changes (and the CS# pin is used).
+ self.mosidata = self.misodata = self.bitcount= 0
# Ignore sample if the clock pin hasn't changed.
if sck == self.oldsck:
self.handle_bit(miso, mosi, sck, cs)
def decode(self, ss, es, data):
+ if self.samplerate is None:
+ raise Exception("Cannot decode without samplerate.")
# TODO: Either MISO or MOSI could be optional. CS# is optional.
for (self.samplenum, pins) in data:
if self.oldpins == pins:
continue
self.oldpins, (miso, mosi, sck, cs) = pins, pins
+ self.have_cs = (cs in (0, 1))
# State machine.
if self.state == 'IDLE':