spi/nrf24l01/uart: Use ChannelError exception.

[libsigrokdecode.git] / decoders / spi / pd.py

diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py
index d0e3409a6c8241eafe32001f496720f3180bdfba..97d5571c066a3d8ec6664de9ef04cc766b4d756b 100644 (file)
--- a/decoders/spi/pd.py
+++ b/decoders/spi/pd.py
@@ -24,15 +24,15 @@ import sigrokdecode as srd
 '''
 OUTPUT_PYTHON format:
 
-SPI packet:
-[<cmd>, <data1>, <data2>]
+Packet:
+[<ptype>, <data1>, <data2>]
 
-Commands:
- - 'DATA': <data1> contains the MISO data, <data2> contains the MOSI data.
+<ptype>:
+ - 'DATA': <data1> contains the MOSI data, <data2> contains the MISO data.
    The data is _usually_ 8 bits (but can also be fewer or more bits).
    Both data items are Python numbers (not strings), or None if the respective
-   probe was not supplied.
- - 'BITS': <data1>/<data2> contain a list of bit values in this MISO/MOSI data
+   channel was not supplied.
+ - 'BITS': <data1>/<data2> contain a list of bit values in this MOSI/MISO data
    item, and for each of those also their respective start-/endsample numbers.
  - 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
    Both data items are Python numbers (0/1), not strings.
@@ -60,8 +60,14 @@ spi_mode = {
     (1, 1): 3, # Mode 3
 }
 
+class SamplerateError(Exception):
+    pass
+
+class ChannelError(Exception):
+    pass
+
 class Decoder(srd.Decoder):
-    api_version = 1
+    api_version = 2
     id = 'spi'
     name = 'SPI'
     longname = 'Serial Peripheral Interface'
@@ -69,10 +75,10 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['spi']
-    probes = (
+    channels = (
         {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'},
     )
-    optional_probes = (
+    optional_channels = (
         {'id': 'miso', 'name': 'MISO', 'desc': 'Master in, slave out'},
         {'id': 'mosi', 'name': 'MOSI', 'desc': 'Master out, slave in'},
         {'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'},
@@ -84,9 +90,9 @@ class Decoder(srd.Decoder):
             'values': (0, 1)},
         {'id': 'cpha', 'desc': 'Clock phase', 'default': 0,
             'values': (0, 1)},
-        {'id': 'bitorder', 'desc': 'Bit order within the SPI data',
+        {'id': 'bitorder', 'desc': 'Bit order',
             'default': 'msb-first', 'values': ('msb-first', 'lsb-first')},
-        {'id': 'wordsize', 'desc': 'Word size of SPI data', 'default': 8},
+        {'id': 'wordsize', 'desc': 'Word size', 'default': 8},
     )
     annotations = (
         ('miso-data', 'MISO data'),
@@ -116,7 +122,6 @@ class Decoder(srd.Decoder):
         self.oldcs = -1
         self.oldpins = None
         self.have_cs = self.have_miso = self.have_mosi = None
-        self.state = 'IDLE'
 
     def metadata(self, key, value):
         if key == srd.SRD_CONF_SAMPLERATE:
@@ -174,9 +179,7 @@ class Decoder(srd.Decoder):
             self.cs_was_deasserted = False
             if self.have_cs:
                 active_low = (self.options['cs_polarity'] == 'active-low')
-                deasserted = (cs == 1) if active_low else (cs == 0)
-                if deasserted:
-                    self.cs_was_deasserted = True
+                self.cs_was_deasserted = (cs == 1) if active_low else (cs == 0)
 
         ws = self.options['wordsize']
 
@@ -261,8 +264,8 @@ class Decoder(srd.Decoder):
         self.handle_bit(miso, mosi, clk, cs)
 
     def decode(self, ss, es, data):
-        if self.samplerate is None:
-            raise Exception("Cannot decode without samplerate.")
+        if not self.samplerate:
+            raise SamplerateError('Cannot decode without samplerate.')
         # Either MISO or MOSI can be omitted (but not both). CS# is optional.
         for (self.samplenum, pins) in data:
 
@@ -276,11 +279,6 @@ class Decoder(srd.Decoder):
 
             # Either MISO or MOSI (but not both) can be omitted.
             if not (self.have_miso or self.have_mosi):
-                raise Exception('Either MISO or MOSI (or both) pins required.')
-
-            # State machine.
-            if self.state == 'IDLE':
-                self.find_clk_edge(miso, mosi, clk, cs)
-            else:
-                raise Exception('Invalid state: %s' % self.state)
+                raise ChannelError('Either MISO or MOSI (or both) pins required.')
 
+            self.find_clk_edge(miso, mosi, clk, cs)