spi: Use/store bits in MSB-first order.

[libsigrokdecode.git] / decoders / spi / pd.py

diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py
index 2d971d31c4fb8657765489f4a6393eb5046f05f9..679335e9489f06ead66c298944a2dea718c1b192 100644 (file)
--- a/decoders/spi/pd.py
+++ b/decoders/spi/pd.py
@@ -42,8 +42,8 @@ Examples:
  ['DATA', 0xff, 0x3a]
  ['BITS', [[1, 80, 82], [1, 83, 84], [1, 85, 86], [1, 87, 88],
            [1, 89, 90], [1, 91, 92], [1, 93, 94], [1, 95, 96]],
-          [[0, 80, 82], [0, 83, 84], [1, 85, 86], [1, 87, 88],
-           [1, 89, 90], [0, 91, 92], [1, 93, 94], [0, 95, 96]]]
+          [[0, 80, 82], [1, 83, 84], [0, 85, 86], [1, 87, 88],
+           [1, 89, 90], [1, 91, 92], [0, 93, 94], [0, 95, 96]]]
  ['DATA', 0x65, 0x00]
  ['DATA', 0xa8, None]
  ['DATA', None, 0x55]
@@ -109,7 +109,7 @@ class Decoder(srd.Decoder):
         self.mosibits = []
         self.startsample = -1
         self.samplenum = -1
-        self.cs_was_deasserted_during_data_word = 0
+        self.cs_was_deasserted = False
         self.oldcs = -1
         self.oldpins = None
         self.have_cs = self.have_miso = self.have_mosi = None
@@ -150,9 +150,11 @@ class Decoder(srd.Decoder):
 
         # Dataword annotations.
         if self.have_miso:
-            self.putw([0, ['%02X' % self.misodata]])
+            ss, es = self.misobits[-1][1], self.misobits[0][2]
+            self.put(ss, es, self.out_ann, [0, ['%02X' % self.misodata]])
         if self.have_mosi:
-            self.putw([1, ['%02X' % self.mosidata]])
+            ss, es = self.mosibits[-1][1], self.mosibits[0][2]
+            self.put(ss, es, self.out_ann, [1, ['%02X' % self.mosidata]])
 
     def reset_decoder_state(self):
         self.misodata = 0 if self.have_miso else None
@@ -165,11 +167,12 @@ class Decoder(srd.Decoder):
         # If this is the first bit of a dataword, save its sample number.
         if self.bitcount == 0:
             self.startsample = self.samplenum
+            self.cs_was_deasserted = False
             if self.have_cs:
                 active_low = (self.options['cs_polarity'] == 'active-low')
-                deasserted = cs if active_low else not cs
+                deasserted = (cs == 1) if active_low else (cs == 0)
                 if deasserted:
-                    self.cs_was_deasserted_during_data_word = 1
+                    self.cs_was_deasserted = True
 
         ws = self.options['wordsize']
 
@@ -187,20 +190,20 @@ class Decoder(srd.Decoder):
             else:
                 self.mosidata |= mosi << self.bitcount
 
-        # Guesstimate the endsample for this bit (can be overridden later).
+        # Guesstimate the endsample for this bit (can be overridden below).
         es = self.samplenum
         if self.bitcount > 0:
-            es += self.samplenum - self.misobits[self.bitcount - 1][1]
+            es += self.samplenum - self.misobits[0][1]
 
         if self.have_miso:
-            self.misobits.append([miso, self.samplenum, es])
+            self.misobits.insert(0, [miso, self.samplenum, es])
         if self.have_mosi:
-            self.mosibits.append([mosi, self.samplenum, es])
+            self.mosibits.insert(0, [mosi, self.samplenum, es])
 
         if self.bitcount > 0 and self.have_miso:
-            self.misobits[self.bitcount - 1][2] = self.samplenum
+            self.misobits[1][2] = self.samplenum
         if self.bitcount > 0 and self.have_mosi:
-            self.mosibits[self.bitcount - 1][2] = self.samplenum
+            self.mosibits[1][2] = self.samplenum
 
         self.bitcount += 1
 
@@ -216,7 +219,7 @@ class Decoder(srd.Decoder):
         bitrate = int(1 / elapsed * self.options['wordsize'])
         self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate)
 
-        if self.have_cs and self.cs_was_deasserted_during_data_word:
+        if self.have_cs and self.cs_was_deasserted:
             self.putw([4, ['CS# was deasserted during this data word!']])
 
         self.reset_decoder_state()
@@ -264,6 +267,10 @@ class Decoder(srd.Decoder):
             self.have_mosi = (mosi in (0, 1))
             self.have_cs = (cs in (0, 1))
 
+            # Either MISO or MOSI (but not both) can be omitted.
+            if not (self.have_miso or self.have_mosi):
+                raise Exception('Either MISO or MOSI (or both) pins required.')
+
             # State machine.
             if self.state == 'IDLE':
                 self.find_clk_edge(miso, mosi, clk, cs)