- self.oldsck = sck
-
- # Sample data on rising/falling clock edge (depends on mode).
- mode = spi_mode[self.options['cpol'], self.options['cpha']]
- if mode == 0 and sck == 0: # Sample on rising clock edge
- continue
- elif mode == 1 and sck == 1: # Sample on falling clock edge
- continue
- elif mode == 2 and sck == 1: # Sample on falling clock edge
- continue
- elif mode == 3 and sck == 0: # Sample on rising clock edge
- continue
-
- # If this is the first bit, save its sample number.
- if self.bitcount == 0:
- self.start_sample = self.samplenum
- active_low = (self.options['cs_polarity'] == 'active-low')
- deasserted = cs if active_low else not cs
- if deasserted:
- self.cs_was_deasserted_during_data_word = 1
-
- ws = self.options['wordsize']
-
- # Receive MOSI bit into our shift register.
+ if self.have_miso:
+ ss, es = self.misobits[-1][1], self.misobits[0][2]
+ bdata = so.to_bytes(self.bw, byteorder='big')
+ self.put(ss, es, self.out_binary, [0, bdata])
+ if self.have_mosi:
+ ss, es = self.mosibits[-1][1], self.mosibits[0][2]
+ bdata = si.to_bytes(self.bw, byteorder='big')
+ self.put(ss, es, self.out_binary, [1, bdata])
+
+ self.put(ss, es, self.out_python, ['BITS', si_bits, so_bits])
+ self.put(ss, es, self.out_python, ['DATA', si, so])
+
+ if self.have_miso:
+ self.misobytes.append(Data(ss=ss, es=es, val=so))
+ if self.have_mosi:
+ self.mosibytes.append(Data(ss=ss, es=es, val=si))
+
+ # Bit annotations.
+ if self.have_miso:
+ for bit in self.misobits:
+ self.put(bit[1], bit[2], self.out_ann, [2, ['%d' % bit[0]]])
+ if self.have_mosi:
+ for bit in self.mosibits:
+ self.put(bit[1], bit[2], self.out_ann, [3, ['%d' % bit[0]]])
+
+ # Dataword annotations.
+ if self.have_miso:
+ self.put(ss, es, self.out_ann, [0, ['%02X' % self.misodata]])
+ if self.have_mosi:
+ self.put(ss, es, self.out_ann, [1, ['%02X' % self.mosidata]])
+
+ def reset_decoder_state(self):
+ self.misodata = 0 if self.have_miso else None
+ self.mosidata = 0 if self.have_mosi else None
+ self.misobits = [] if self.have_miso else None
+ self.mosibits = [] if self.have_mosi else None
+ self.bitcount = 0
+
+ def cs_asserted(self, cs):
+ active_low = (self.options['cs_polarity'] == 'active-low')
+ return (cs == 0) if active_low else (cs == 1)
+
+ def handle_bit(self, miso, mosi, clk, cs):
+ # If this is the first bit of a dataword, save its sample number.
+ if self.bitcount == 0:
+ self.ss_block = self.samplenum
+ self.cs_was_deasserted = \
+ not self.cs_asserted(cs) if self.have_cs else False
+
+ ws = self.options['wordsize']
+
+ # Receive MISO bit into our shift register.
+ if self.have_miso:
+ if self.options['bitorder'] == 'msb-first':
+ self.misodata |= miso << (ws - 1 - self.bitcount)
+ else:
+ self.misodata |= miso << self.bitcount
+
+ # Receive MOSI bit into our shift register.
+ if self.have_mosi: