rtc8564: Handle register 0x06 (weekday).

[libsigrokdecode.git] / decoders / rtc8564 / pd.py

diff --git a/decoders/rtc8564/pd.py b/decoders/rtc8564/pd.py
index 0aa7952f7ec1cadfd0580ac10346ecc8f6ea5ea6..e919148af911fc1fde17ba2e6cfd3542f59c2d86 100644 (file)
--- a/decoders/rtc8564/pd.py
+++ b/decoders/rtc8564/pd.py
@@ -52,7 +52,13 @@ class Decoder(srd.Decoder):
         ['reg-0x08', 'Register 0x08'],
         ['read', 'Read date/time'],
         ['write', 'Write date/time'],
+        ['bits', 'Bits'],
     ]
+    annotation_rows = (
+        ('bits', 'Bits', (11,)),
+        ('regs', 'Registers', tuple(range(0, 8 + 1))),
+        ('date-time', 'Date/time', (9, 10)),
+    )
 
     def __init__(self, **kwargs):
         self.state = 'IDLE'
@@ -60,6 +66,7 @@ class Decoder(srd.Decoder):
         self.minutes = -1
         self.seconds = -1
         self.days = -1
+        self.weekdays = -1
         self.months = -1
         self.years = -1
 
@@ -102,7 +109,7 @@ class Decoder(srd.Decoder):
         self.seconds = bcd2int(b & 0x7f)
         self.putx([2, ['Seconds: %d' % self.seconds]])
         vl = 1 if (b & (1 << 7)) else 0
-        self.putx([2, ['Voltage low (VL) bit: %d' % vl]])
+        self.putx([11, ['Voltage low (VL) bit: %d' % vl]])
 
     def handle_reg_0x03(self, b): # Minutes
         self.minutes = bcd2int(b & 0x7f)
@@ -116,8 +123,9 @@ class Decoder(srd.Decoder):
         self.days = bcd2int(b & 0x3f)
         self.putx([5, ['Days: %d' % self.days]])
 
-    def handle_reg_0x06(self, b): # Day counter
-        pass
+    def handle_reg_0x06(self, b): # Weekdays
+        self.weekdays = bcd2int(b & 0x07)
+        self.putx([6, ['Weekdays: %d' % self.weekdays]])
 
     def handle_reg_0x07(self, b): # Months / century
         # TODO: Handle century bit.