avr_isp: Add more parts

[libsigrokdecode.git] / decoders / rtc8564 / pd.py

diff --git a/decoders/rtc8564/pd.py b/decoders/rtc8564/pd.py
index 25eb4e7d7aa85c7c5b6c06144fffa5c4980ae981..d71e62b8b9b268333df9013923885e822aa4369f 100644 (file)
--- a/decoders/rtc8564/pd.py
+++ b/decoders/rtc8564/pd.py
@@ -35,7 +35,7 @@ class Decoder(srd.Decoder):
     desc = 'Realtime clock module protocol.'
     license = 'gplv2+'
     inputs = ['i2c']
-    outputs = ['rtc8564']
+    outputs = []
     tags = ['Clock/timing']
     annotations = reg_list() + (
         ('read', 'Read date/time'),
@@ -48,7 +48,7 @@ class Decoder(srd.Decoder):
     )
     annotation_rows = (
         ('bits', 'Bits', tuple(range(0, 8 + 1)) + (11, 12, 13)),
-        ('regs', 'Register access', (14, 15)),
+        ('regs', 'Register accesses', (14, 15)),
         ('date-time', 'Date/time', (9, 10)),
     )