pjdl: prepare for "stretched" timings

[libsigrokdecode.git] / decoders / pjdl / pd.py

diff --git a/decoders/pjdl/pd.py b/decoders/pjdl/pd.py
index 2d4fb0da2fd9a38505849c62d8bf13e3ff762adc..11f72ab98a99e04d04a64a1f3f5779fdee7ad162 100644 (file)
--- a/decoders/pjdl/pd.py
+++ b/decoders/pjdl/pd.py
@@ -119,7 +119,7 @@ class Decoder(srd.Decoder):
     desc = 'PJDL, a single wire serial link layer for PJON.'
     license = 'gplv2+'
     inputs = ['logic']
-    outputs = ['pjon-link']
+    outputs = ['pjon_link']
     tags = ['Embedded']
     channels = (
         {'id': 'data' , 'name': 'DATA', 'desc': 'Single wire data'},
@@ -387,7 +387,9 @@ class Decoder(srd.Decoder):
         # for bit widths (tolerance margin).
 
         # Get times in microseconds.
-        self.data_width, self.pad_width = self.mode_times[self.options['mode']]
+        mode_times = self.mode_times[self.options['mode']]
+        mode_times = [t * 1.0 for t in mode_times]
+        self.data_width, self.pad_width = mode_times
         self.byte_width = self.pad_width + 9 * self.data_width
         self.add_idle_width = self.options['idle_add_us']
         self.idle_width = self.byte_width + self.add_idle_width