# Common variables
self.samplenum = 0
# Link layer variables
- self.lnk_state = 'WAIT FOR EVENT'
+ self.lnk_state = 'WAIT FOR NEGEDGE'
self.lnk_event = 'NONE'
self.lnk_start = -1
self.lnk_bit = -1
def start(self, metadata):
self.samplerate = metadata['samplerate']
self.out_proto = self.add(srd.OUTPUT_PROTO, 'onewire')
- self.out_ann = self.add(srd.OUTPUT_ANN, 'onewire')
+ self.out_ann = self.add(srd.OUTPUT_ANN , 'onewire')
# The width of the 1-Wire time base (30us) in number of samples.
# TODO: optimize this value
def report(self):
pass
- def get_data_sample(self, owr):
- # Skip samples until we're in the middle of the start bit.
- if not self.reached_data_sample():
- return
-
- self.data_sample = owr
-
- self.cur_data_bit = 0
- self.databyte = 0
- self.startsample = -1
-
- self.state = 'GET DATA BITS'
-
- self.put(self.cycle_start, self.samplenum, self.out_proto,
- ['STARTBIT', self.startbit])
- self.put(self.cycle_start, self.samplenum, self.out_ann,
- [ANN_ASCII, ['Start bit', 'Start', 'S']])
-
- def get_data_bits(self, owr):
- # Skip samples until we're in the middle of the desired data bit.
- if not self.reached_bit(self.cur_data_bit + 1):
- return
-
- # Save the sample number where the data byte starts.
- if self.startsample == -1:
- self.startsample = self.samplenum
-
- # Get the next data bit in LSB-first or MSB-first fashion.
- if self.options['bit_order'] == 'lsb-first':
- self.databyte >>= 1
- self.databyte |= \
- (owr << (self.options['num_data_bits'] - 1))
- elif self.options['bit_order'] == 'msb-first':
- self.databyte <<= 1
- self.databyte |= (owr << 0)
- else:
- raise Exception('Invalid bit order value: %s',
- self.options['bit_order'])
-
- # Return here, unless we already received all data bits.
- # TODO? Off-by-one?
- if self.cur_data_bit < self.options['num_data_bits'] - 1:
- self.cur_data_bit += 1
- return
-
- self.state = 'GET PARITY BIT'
-
- self.put(self.startsample, self.samplenum - 1, self.out_proto,
- ['DATA', self.databyte])
-
- self.putx([ANN_ASCII, [chr(self.databyte)]])
- self.putx([ANN_DEC, [str(self.databyte)]])
- self.putx([ANN_HEX, [hex(self.databyte),
- hex(self.databyte)[2:]]])
- self.putx([ANN_OCT, [oct(self.databyte),
- oct(self.databyte)[2:]]])
- self.putx([ANN_BITS, [bin(self.databyte),
- bin(self.databyte)[2:]]])
-
def decode(self, ss, es, data):
- for (self.samplenum, owr) in data:
-
- # First sample: Save OWR value.
- if self.oldbit == None:
- self.oldbit = owr
- continue
+ for (self.samplenum, (owr, pwr)) in data:
# Data link layer
+
+ # Clear events.
+ self.lnk_event = "RESET"
+ # State machine.
if self.lnk_state == 'WAIT FOR FALLING EDGE':
# The start of a cycle is a falling edge.
- if (old_owr == 1 and owr == 0):
- # Save the sample number where the start bit begins.
- self.lnk_start = self.samplenum
+ if (owr == 0):
+ # Save the sample number for the falling edge.
+ self.lnk_fall = self.samplenum
# Go to waiting for sample time
- self.lnk_state = 'WAIT FOR SAMPLE'
- elif self.lnk_state == 'WAIT FOR SAMPLE':
+ self.lnk_state = 'WAIT FOR DATA SAMPLE'
+ elif self.lnk_state == 'WAIT FOR DATA SAMPLE':
# Data should be sample one 'time unit' after a falling edge
- if (self.samplenum == self.lnk_start + self.time_base):
+ if (self.samplenum - self.lnk_fall == 1*self.time_base):
self.lnk_bit = owr & 0x1
- self.lnk_cnt = self.lnk_cnt + 1
- self.lnk_byte = (self.lnk_byte << 1) & self.lnk_bit
- self.lnk_state = 'WAIT FOR RISING EDGE'
+ self.lnk_event = "DATA BIT"
+ if (self.lnk_bit) : self.lnk_state = 'WAIT FOR FALLING EDGE'
+ else : self.lnk_state = 'WAIT FOR RISING EDGE'
elif self.lnk_state == 'WAIT FOR RISING EDGE':
# The end of a cycle is a rising edge.
- if (old_owr == 0 and owr == 1):
- # Data bit cycle length should be between 2*T and
- if (self.samplenum < self.lnk_start + 2*self.time_base):
- if (self.lnk_cnt == 8)
- self.put(self.startsample, self.samplenum - 1, self.out_proto, ['BYTE', self.lnk_byte])
- self.lnk_cnt = 0
- if (self.samplenum == self.lnk_start + 8*self.time_base):
- self.put(self.startsample, self.samplenum - 1, self.out_proto, ['RESET'])
-
- # Go to waiting for sample time
- self.lnk_state = 'WAIT FOR SAMPLE'
-
- elif self.state_lnk == 'GET DATA BITS' : self.get_data_bits(owr)
- else : raise Exception('Invalid state: %d' % self.state)
-
- # Save current RX/TX values for the next round.
- self.oldbit = owr
-
+ if (owr == 1):
+ # A reset cycle is longer than 8T
+ if (self.samplenum - self.lnk_fall > 8*self.time_base):
+ # Save the sample number for the falling edge.
+ self.lnk_rise = self.samplenum
+ # Send a reset event to the next protocol layer
+ self.lnk_event = "RESET"
+ self.lnk_state = "WAIT FOR PRESENCE DETECT"
+ elif self.lnk_state == 'WAIT FOR PRESENCE DETECT':
+ # Data should be sample one 'time unit' after a falling edge
+ if (self.samplenum - self.lnk_rise == 2.5*self.time_base):
+ self.lnk_bit = owr & 0x1
+ self.lnk_event = "PRESENCE DETECT"
+ if (self.lnk_bit) : self.lnk_state = 'WAIT FOR FALLING EDGE'
+ else : self.lnk_state = 'WAIT FOR RISING EDGE'
+ else:
+ raise Exception('Invalid lnk_state: %s' % self.lnk_state)
+
+ # Network layer
+
+ # Clear events.
+ self.net_event = "RESET"
+ # State machine.
+ if (self.lnk_event == "RESET"):
+ self.net_state = "WAIT FOR COMMAND"
+ self.net_cnt = 0
+ self.net_cmd = 0
+ elif (self.lnk_event == "DATA BIT"):
+ if (self.net_state == "WAIT FOR COMMAND"):
+ self.net_cnt = self.net_cnt + 1
+ self.net_cmd = (self.net_cmd << 1) & self.lnk_bit
+ if (self.lnk_cnt == 8):
+ self.put(self.startsample, self.samplenum, self.out_proto, ['LNK: BYTE', self.lnk_byte])
+ self.put(self.startsample, self.samplenum, self.out_ann , ['LNK: BYTE', self.lnk_byte])
+ if (self.net_cmd == 0x33):
+ # READ ROM
+ break
+ elif (self.net_cmd == 0x0f):
+ # READ ROM
+ break
+ elif (self.net_cmd == 0xcc):
+ # SKIP ROM
+ break
+ elif (self.net_cmd == 0x55):
+ # MATCH ROM
+ break
+ elif (self.net_cmd == 0xf0):
+ # SEARCH ROM
+ break
+ elif (self.net_cmd == 0x3c):
+ # OVERDRIVE SKIP ROM
+ break
+ elif (self.net_cmd == 0x69):
+ # OVERDRIVE MATCH ROM
+ break
+ self.lnk_cnt = 0
+ if (self.net_state == "WAIT FOR ROM"):
+ #
+ break
+ else:
+ raise Exception('Invalid net_state: %s' % self.net_state)
+ elif not (self.lnk_event == "NONE"):
+ raise Exception('Invalid net_event: %s' % self.net_event)
+
+
+
+# if (self.samplenum == self.lnk_start + 8*self.time_base):
+# self.put(self.startsample, self.samplenum - 1, self.out_proto, ['RESET'])
projects / libsigrokdecode.git / blobdiff