## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-# LPC protocol decoder
-
import sigrokdecode as srd
# ...
outputs = ['lpc']
probes = [
{'id': 'lframe', 'name': 'LFRAME#', 'desc': 'TODO'},
- {'id': 'lreset', 'name': 'LRESET#', 'desc': 'TODO'},
{'id': 'lclk', 'name': 'LCLK', 'desc': 'TODO'},
{'id': 'lad0', 'name': 'LAD[0]', 'desc': 'TODO'},
{'id': 'lad1', 'name': 'LAD[1]', 'desc': 'TODO'},
{'id': 'lad3', 'name': 'LAD[3]', 'desc': 'TODO'},
]
optional_probes = [
+ {'id': 'lreset', 'name': 'LRESET#', 'desc': 'TODO'},
{'id': 'ldrq', 'name': 'LDRQ#', 'desc': 'TODO'},
{'id': 'serirq', 'name': 'SERIRQ', 'desc': 'TODO'},
{'id': 'clkrun', 'name': 'CLKRUN#', 'desc': 'TODO'},
]
options = {}
annotations = [
- ['Text', 'Human-readable text'],
+ ['warnings', 'Warnings'],
+ ['start', 'Start'],
+ ['cycle-type', 'Cycle-type/direction'],
+ ['addr', 'Address'],
+ ['tar1', 'Turn-around cycle 1'],
+ ['sync', 'Sync'],
+ ['data', 'Data'],
+ ['tar2', 'Turn-around cycle 2'],
]
def __init__(self, **kwargs):
self.tarcount = 0
self.synccount = 0
self.oldpins = None
+ self.ss_block = self.es_block = None
- def start(self, metadata):
- # self.out_proto = self.add(srd.OUTPUT_PROTO, 'lpc')
- self.out_ann = self.add(srd.OUTPUT_ANN, 'lpc')
-
- def report(self):
- pass
+ def start(self):
+ # self.out_proto = self.register(srd.OUTPUT_PYTHON)
+ self.out_ann = self.register(srd.OUTPUT_ANN)
def putb(self, data):
- self.put(0, 0, self.out_ann, data)
+ self.put(self.ss_block, self.es_block, self.out_ann, data)
def handle_get_start(self, lad, lad_bits, lframe):
# LAD[3:0]: START field (1 clock cycle).
# the peripherals must use. However, the host can keep LFRAME# asserted
# multiple clocks, and we output all START fields that occur, even
# though the peripherals are supposed to ignore all but the last one.
- s = fields['START'][lad]
- self.putb([0, [s]])
+ self.es_block = self.samplenum
+ self.putb([1, [fields['START'][lad], 'START', 'St', 'S']])
+ self.ss_block = self.samplenum
# Output a warning if LAD[3:0] changes while LFRAME# is low.
# TODO
if (self.lad != -1 and self.lad != lad):
- self.putb([0, ['Warning: LAD[3:0] changed while '
- 'LFRAME# was asserted']])
+ self.putb([0, ['LAD[3:0] changed while LFRAME# was asserted']])
# LFRAME# is asserted (low). Wait until it gets de-asserted again
# (the host is allowed to keep it asserted multiple clocks).
# TODO: Warning/error on invalid cycle types.
if self.cycle_type == 'Reserved':
- self.putb([0, ['Warning: Invalid cycle type (%s)' % lad_bits]])
+ self.putb([0, ['Invalid cycle type (%s)' % lad_bits]])
- # ...
- self.putb([0, ['Cycle type: %s' % self.cycle_type]])
+ self.es_block = self.samplenum
+ self.putb([2, ['Cycle type: %s' % self.cycle_type]])
+ self.ss_block = self.samplenum
self.state = 'GET ADDR'
self.addr = 0
self.cur_nibble += 1
return
+ self.es_block = self.samplenum
s = 'Address: 0x%%0%dx' % addr_nibbles
- self.putb([0, [s % self.addr]])
+ self.putb([3, [s % self.addr]])
+ self.ss_block = self.samplenum
self.state = 'GET TAR'
self.tar_count = 0
def handle_get_tar(self, lad, lad_bits):
# LAD[3:0]: First TAR (turn-around) field (2 clock cycles).
- self.putb([0, ['TAR, cycle %d: %s' % (self.tarcount, lad_bits)]])
+ self.es_block = self.samplenum
+ self.putb([4, ['TAR, cycle %d: %s' % (self.tarcount, lad_bits)]])
+ self.ss_block = self.samplenum
# On the first TAR clock cycle LAD[3:0] is driven to 1111 by
# either the host or peripheral. On the second clock cycle,
# the host or peripheral tri-states LAD[3:0], but its value
# should still be 1111, due to pull-ups on the LAD lines.
if lad_bits != '1111':
- self.putb([0, ['Warning: TAR, cycle %d: %s (expected 1111)' % \
+ self.putb([0, ['TAR, cycle %d: %s (expected 1111)' % \
(self.tarcount, lad_bits)]])
if (self.tarcount != 1):
# TODO: Warnings if reserved value are seen?
if self.cycle_type == 'Reserved':
- self.putb([0, ['Warning: SYNC, cycle %d: %s (reserved value)' % \
+ self.putb([0, ['SYNC, cycle %d: %s (reserved value)' % \
(self.synccount, self.sync_val)]])
- self.putb([0, ['SYNC, cycle %d: %s' % (self.synccount, self.sync_val)]])
+ self.es_block = self.samplenum
+ self.putb([5, ['SYNC, cycle %d: %s' % (self.synccount, self.sync_val)]])
+ self.ss_block = self.samplenum
# TODO
self.cycle_count += 1
return
- self.putb([0, ['DATA: 0x%02x' % self.databyte]])
+ self.es_block = self.samplenum
+ self.putb([6, ['DATA: 0x%02x' % self.databyte]])
+ self.ss_block = self.samplenum
self.cycle_count = 0
self.state = 'GET TAR2'
def handle_get_tar2(self, lad, lad_bits):
# LAD[3:0]: Second TAR field (2 clock cycles).
- self.putb([0, ['TAR, cycle %d: %s' % (self.tarcount, lad_bits)]])
+ self.es_block = self.samplenum
+ self.putb([7, ['TAR, cycle %d: %s' % (self.tarcount, lad_bits)]])
+ self.ss_block = self.samplenum
# On the first TAR clock cycle LAD[3:0] is driven to 1111 by
# either the host or peripheral. On the second clock cycle,
self.state = 'IDLE'
def decode(self, ss, es, data):
- for (samplenum, pins) in data:
+ for (self.samplenum, pins) in data:
# If none of the pins changed, there's nothing to do.
if self.oldpins == pins:
self.oldpins = pins
# Get individual pin values into local variables.
- (lframe, lreset, lclk, lad0, lad1, lad2, lad3) = pins[:7]
- (ldrq, serirq, clkrun, lpme, lpcpd, lsmi) = pins[7:]
+ (lframe, lclk, lad0, lad1, lad2, lad3) = pins[:6]
+ (lreset, ldrq, serirq, clkrun, lpme, lpcpd, lsmi) = pins[6:]
# Only look at the signals upon rising LCLK edges. The LPC clock
# is the same as the PCI clock (which is sampled at rising edges).
# A valid LPC cycle starts with LFRAME# being asserted (low).
if lframe != 0:
continue
+ self.ss_block = self.samplenum
self.state = 'GET START'
self.lad = -1
# self.clocknum = 0
projects / libsigrokdecode.git / blobdiff