All PDs: Consistent naming/case for annotation shortnames/IDs.

[libsigrokdecode.git] / decoders / jtag_stm32 / pd.py

diff --git a/decoders/jtag_stm32/pd.py b/decoders/jtag_stm32/pd.py
index e30788c7dfc348b696213a25a2bc49014eb3798b..3928ae36ca45fa35ab83015e363fa83dadb5a0d6 100644 (file)
--- a/decoders/jtag_stm32/pd.py
+++ b/decoders/jtag_stm32/pd.py
@@ -1,5 +1,5 @@
 ##
-## This file is part of the sigrok project.
+## This file is part of the libsigrokdecode project.
 ##
 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
 ##
@@ -18,8 +18,6 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-# ST STM32 JTAG protocol decoder
-
 import sigrokdecode as srd
 
 # JTAG debug port data registers (in IR[3:0]) and their sizes (in bits)
@@ -133,19 +131,16 @@ class Decoder(srd.Decoder):
     optional_probes = []
     options = {}
     annotations = [
-        ['Text', 'Human-readable text'],
+        ['text', 'Human-readable text'],
     ]
 
     def __init__(self, **kwargs):
         self.state = 'IDLE'
         # self.state = 'BYPASS'
 
-    def start(self, metadata):
-        # self.out_proto = self.add(srd.OUTPUT_PROTO, 'jtag_stm32')
-        self.out_ann = self.add(srd.OUTPUT_ANN, 'jtag_stm32')
-
-    def report(self):
-        pass
+    def start(self):
+        # self.out_proto = self.register(srd.OUTPUT_PYTHON)
+        self.out_ann = self.register(srd.OUTPUT_ANN)
 
     def handle_reg_bypass(self, cmd, bits):
         # TODO