]> sigrok.org Git - libsigrokdecode.git/blobdiff - decoders/jtag_ejtag/pd.py
decoders: Add/update tags for each PD.
[libsigrokdecode.git] / decoders / jtag_ejtag / pd.py
index 80888edeaabb8d422651e2416a89b54f844d9413..0bffde87bb517ca7884e7c1c54b17ded46a4b39c 100644 (file)
@@ -197,6 +197,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['jtag']
     outputs = ['jtag_ejtag']
+    tags = ['Debug/trace']
     annotations = (
         ('instruction', 'Instruction'),
     ) + regs_items['ann'] + (
@@ -223,7 +224,7 @@ class Decoder(srd.Decoder):
         self.put(self.ss, self.es, self.out_ann, data)
 
     def put_at(self, ss: int, es: int, data):
-        self.put(ss, es, self.out_ann, data);
+        self.put(ss, es, self.out_ann, data)
 
     def start(self):
         self.out_ann = self.register(srd.OUTPUT_ANN)
@@ -243,24 +244,23 @@ class Decoder(srd.Decoder):
         ss, es = self.pracc_state.ss, self.pracc_state.es
         pracc_write = (control_out & ControlReg.PRNW) != 0
 
-        display_string = 'PrAcc: '
-        display_string += 'Store' if pracc_write else 'Load/Fetch'
+        s = 'PrAcc: '
+        s += 'Store' if pracc_write else 'Load/Fetch'
 
         if pracc_write:
-            if self.pracc_state.address_out != None:
-                display_string += ', A:' + ' 0x{:08X}'.format(self.pracc_state.address_out)
-            if self.pracc_state.data_out != None:
-                display_string += ', D:' + ' 0x{:08X}'.format(self.pracc_state.data_out)
+            if self.pracc_state.address_out is not None:
+                s += ', A:' + ' 0x{:08X}'.format(self.pracc_state.address_out)
+            if self.pracc_state.data_out is not None:
+                s += ', D:' + ' 0x{:08X}'.format(self.pracc_state.data_out)
         else:
-            if self.pracc_state.address_out != None:
-                display_string += ', A:' + ' 0x{:08X}'.format(self.pracc_state.address_out)
-            if self.pracc_state.data_in != None:
-                display_string += ', D:' + ' 0x{:08X}'.format(self.pracc_state.data_in)
+            if self.pracc_state.address_out is not None:
+                s += ', A:' + ' 0x{:08X}'.format(self.pracc_state.address_out)
+            if self.pracc_state.data_in is not None:
+                s += ', D:' + ' 0x{:08X}'.format(self.pracc_state.data_in)
 
         self.pracc_state.reset()
 
-        display_data = [Ann.PRACC, [display_string]]
-        self.put_at(ss, es, display_data)
+        self.put_at(ss, es, [Ann.PRACC, [s]])
 
     def parse_control_reg(self, ann):
         reg_write = ann == Ann.CONTROL_FIELD_IN
@@ -292,9 +292,8 @@ class Decoder(srd.Decoder):
 
             short_desc = comment + ': ' + value_str
             long_desc = value_descriptions[value_index] if len(value_descriptions) > value_index else '?'
-            display_data = [ann, [long_desc, short_desc]]
 
-            self.put_at(ss, es, display_data)
+            self.put_at(ss, es, [ann, [long_desc, short_desc]])
 
     def check_last_data(self):
         if not hasattr(self, 'last_data'):
@@ -359,16 +358,16 @@ class Decoder(srd.Decoder):
 
     def handle_ir_tdi(self, val):
         code = bin2int(val[0])
-        hex = '0x{:02X}'.format(code)
+        hexval = '0x{:02X}'.format(code)
         if code in ejtag_insn:
             # Format instruction name.
             insn = ejtag_insn[code]
             s_short = insn[0]
-            s_long = insn[0] + ': ' + insn[1] + ' (' + hex + ')'
+            s_long = insn[0] + ': ' + insn[1] + ' (' + hexval + ')'
             # Display it and select data register.
             self.put_current([Ann.INSTRUCTION, [s_long, s_short]])
         else:
-            self.put_current([Ann.INSTRUCTION, [hex, 'IR TDI ({})'.format(hex)]])
+            self.put_current([Ann.INSTRUCTION, [hexval, 'IR TDI ({})'.format(hexval)]])
         self.select_reg(code)
 
     def handle_new_state(self, new_state):