configure.ac/Makefile.am: Alphabetical order.

[libsigrokdecode.git] / decoders / jtag / jtag.py

diff --git a/decoders/jtag/jtag.py b/decoders/jtag/jtag.py
index 197d5a65462369683f2b073bbfa91d3d8f49541f..4e27ce8477cdb09d48214f7143e81b093efbccce 100644 (file)
--- a/decoders/jtag/jtag.py
+++ b/decoders/jtag/jtag.py
@@ -26,7 +26,7 @@ class Decoder(srd.Decoder):
     api_version = 1
     id = 'jtag'
     name = 'JTAG'
-    longname = 'Joint Test Action Group'
+    longname = 'Joint Test Action Group (IEEE 1149.1)'
     desc = 'Protocol for testing, debugging, and flashing ICs.'
     license = 'gplv2+'
     inputs = ['logic']
@@ -38,12 +38,13 @@ class Decoder(srd.Decoder):
         {'id': 'tms',  'name': 'TMS',  'desc': 'Test mode select'},
     ]
     optional_probes = [
-        # {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'},
-        # {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'},
+        {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'},
+        {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'},
+        {'id': 'rtck', 'name': 'RTCK',  'desc': 'Return clock signal'},
     ]
     options = {}
     annotations = [
-        ['ASCII', 'TODO: description'],
+        ['Text', 'Human-readable text'],
     ]
 
     def __init__(self, **kwargs):
@@ -133,14 +134,16 @@ class Decoder(srd.Decoder):
 
             t = self.state[-2:] + ' TDI'
             b = ''.join(map(str, self.bits_tdi))
-            s = t + ': ' + b + ', ' + str(len(self.bits_tdi)) + ' bits'
+            h = ' (0x%x' % int('0b' + b, 2) + ')'
+            s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi)) + ' bits'
             self.put(self.ss, self.es, self.out_ann, [0, [s]])
             self.put(self.ss, self.es, self.out_proto, [t, b])
             self.bits_tdi = []
 
             t = self.state[-2:] + ' TDO'
             b = ''.join(map(str, self.bits_tdo))
-            s = t + ': ' + b + ', ' + str(len(self.bits_tdo)) + ' bits'
+            h = ' (0x%x' % int('0b' + b, 2) + ')'
+            s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo)) + ' bits'
             self.put(self.ss, self.es, self.out_ann, [0, [s]])
             self.put(self.ss, self.es, self.out_proto, [t, b])
             self.bits_tdo = []
@@ -156,8 +159,8 @@ class Decoder(srd.Decoder):
             self.oldpins = pins
 
             # Get individual pin values into local variables.
-            # TODO: Handle optional pins (TRST, SRST).
-            (tdi, tdo, tck, tms) = pins
+            # Unused probes will have a value of > 1.
+            (tdi, tdo, tck, tms, trst, srst, rtck) = pins
 
             # We only care about TCK edges (either rising or falling).
             if (self.oldtck == tck):