command. Slave addresses do not include bit 0 (the READ/WRITE indication bit).
For example, a slave address field could be 0x51 (instead of 0xa2).
For 'START', 'START REPEAT', 'STOP', 'ACK', and 'NACK' <pdata> is None.
+For 'BITS' <pdata> is a sequence of tuples of bit values and their start and
+stop positions, in LSB first order (although the I2C protocol is MSB first).
'''
# Meaning of table items:
'ADDRESS WRITE': [7, 'Address write: {b:02X}', 'AW: {b:02X}', '{b:02X}'],
'DATA READ': [8, 'Data read: {b:02X}', 'DR: {b:02X}', '{b:02X}'],
'DATA WRITE': [9, 'Data write: {b:02X}', 'DW: {b:02X}', '{b:02X}'],
+ 'WARN': [10, '{text}'],
}
class Decoder(srd.Decoder):
def reset(self):
self.samplerate = None
- self.ss = self.es = self.ss_byte = -1
self.is_write = None
self.rem_addr_bytes = None
+ self.slave_addr_7 = None
+ self.slave_addr_10 = None
self.is_repeat_start = False
- self.state = 'FIND START'
self.pdu_start = None
self.pdu_bits = 0
self.data_bits = []
+ self.bitwidth = 0
def metadata(self, key, value):
if key == srd.SRD_CONF_SAMPLERATE:
self.out_bitrate = self.register(srd.OUTPUT_META,
meta=(int, 'Bitrate', 'Bitrate from Start bit to Stop bit'))
- def putx(self, data):
- self.put(self.ss, self.es, self.out_ann, data)
+ def putg(self, ss, es, cls, text):
+ self.put(ss, es, self.out_ann, [cls, text])
- def putp(self, data):
- self.put(self.ss, self.es, self.out_python, data)
+ def putp(self, ss, es, data):
+ self.put(ss, es, self.out_python, data)
- def putb(self, data):
- self.put(self.ss, self.es, self.out_binary, data)
+ def putb(self, ss, es, data):
+ self.put(ss, es, self.out_binary, data)
- def handle_start(self, pins):
- self.ss, self.es = self.samplenum, self.samplenum
+ def _wants_start(self):
+ # Check whether START is required (to sync to the input stream).
+ return self.pdu_start is None
+
+ def _collects_address(self):
+ # Check whether the transfer still is in the address phase (is
+ # still collecting address and r/w details, or has not started
+ # collecting it).
+ return self.rem_addr_bytes is None or self.rem_addr_bytes != 0
+
+ def _collects_byte(self):
+ # Check whether bits of a byte are being collected. Outside of
+ # the data byte, the bit is the ACK/NAK slot.
+ return self.data_bits is None or len(self.data_bits) < 8
+
+ def handle_start(self, ss, es):
if self.is_repeat_start:
cmd = 'START REPEAT'
else:
cmd = 'START'
- self.pdu_start = self.samplenum
+ self.pdu_start = ss
self.pdu_bits = 0
- self.putp([cmd, None])
+ self.putp(ss, es, [cmd, None])
cls, texts = proto[cmd][0], proto[cmd][1:]
- self.putx([cls, texts])
- self.state = 'FIND ADDRESS'
+ self.putg(ss, es, cls, texts)
self.is_repeat_start = True
self.is_write = None
+ self.slave_addr_7 = None
+ self.slave_addr_10 = None
self.rem_addr_bytes = None
self.data_bits.clear()
+ self.bitwidth = 0
# Gather 8 bits of data plus the ACK/NACK bit.
- def handle_address_or_data(self, pins):
- scl, sda = pins
+ def handle_address_or_data(self, ss, es, value):
self.pdu_bits += 1
# Accumulate a byte's bits, including its start position.
# the bit value gets sampled. Assume the start of the next bit
# as the end sample number of the previous bit. Guess the last
# bit's end sample number from the second last bit's width.
- # (gsi: Shouldn't falling SCL be the end of the bit value?)
# Keep the bits in receive order (MSB first) during accumulation.
- if not self.data_bits:
- self.ss_byte = self.samplenum
+ # (gsi: Strictly speaking falling SCL would be the end of the
+ # bit value's validity. That'd break compatibility though.)
if self.data_bits:
- self.data_bits[-1][2] = self.samplenum
- self.data_bits.append([sda, self.samplenum, self.samplenum])
+ self.data_bits[-1][2] = ss
+ self.data_bits.append([value, ss, es])
if len(self.data_bits) < 8:
return
self.bitwidth = self.data_bits[-2][2] - self.data_bits[-3][2]
- self.data_bits[-1][2] += self.bitwidth
+ self.data_bits[-1][2] = self.data_bits[-1][1] + self.bitwidth
# Get the byte value. Address and data are transmitted MSB-first.
d = bitpack_msb(self.data_bits, 0)
- if self.state == 'FIND ADDRESS':
- # The READ/WRITE bit is only in the first address byte, not
- # in data bytes. Address bit pattern 0b1111_0xxx means that
- # this is a 10bit slave address, another byte follows. Get
- # the R/W direction and the address bytes count from the
- # first byte in the I2C transfer.
+ ss_byte, es_byte = self.data_bits[0][1], self.data_bits[-1][2]
+
+ # Process the address bytes at the start of a transfer. The
+ # first byte will carry the R/W bit, and all of the 7bit address
+ # or part of a 10bit address. Bit pattern 0b11110xxx signals
+ # that another byte follows which carries the remaining bits of
+ # a 10bit slave address.
+ is_address = self._collects_address()
+ if is_address:
addr_byte = d
if self.rem_addr_bytes is None:
if (addr_byte & 0xf8) == 0xf0:
self.rem_addr_bytes = 1
self.slave_addr_7 = addr_byte >> 1
self.slave_addr_10 = None
- is_seven = self.slave_addr_7 is not None
+ has_rw_bit = self.is_write is None
if self.is_write is None:
read_bit = bool(addr_byte & 1)
- shift_seven = self.options['address_format'] == 'shifted'
- if is_seven and shift_seven:
- d = d >> 1
+ if self.options['address_format'] == 'shifted':
+ d >>= 1
self.is_write = False if read_bit else True
- else:
+ elif self.slave_addr_10 is not None:
self.slave_addr_10 |= addr_byte
-
+ else:
+ cls, texts = proto['WARN'][0], proto['WARN'][1:]
+ msg = 'Unhandled address byte'
+ texts = [t.format(text = msg) for t in texts]
+ self.putg(ss_byte, es_byte, cls, texts)
+ is_write = self.is_write
+ is_seven = self.slave_addr_7 is not None
+
+ # Determine annotation classes depending on whether the byte is
+ # an address or payload data, and whether it's written or read.
bin_class = -1
- if self.state == 'FIND ADDRESS' and self.is_write:
+ if is_address and is_write:
cmd = 'ADDRESS WRITE'
bin_class = 1
- elif self.state == 'FIND ADDRESS' and not self.is_write:
+ elif is_address and not is_write:
cmd = 'ADDRESS READ'
bin_class = 0
- elif self.state == 'FIND DATA' and self.is_write:
+ elif not is_address and is_write:
cmd = 'DATA WRITE'
bin_class = 3
- elif self.state == 'FIND DATA' and not self.is_write:
+ elif not is_address and not is_write:
cmd = 'DATA READ'
bin_class = 2
- self.ss, self.es = self.ss_byte, self.samplenum + self.bitwidth
-
# Reverse the list of bits to LSB first order before emitting
# annotations and passing bits to upper layers. This may be
# unexpected because the protocol is MSB first, but it keeps
# backwards compatibility.
- self.data_bits.reverse()
- self.putp(['BITS', self.data_bits])
- self.putp([cmd, d])
+ lsb_bits = self.data_bits[:]
+ lsb_bits.reverse()
+ self.putp(ss_byte, es_byte, ['BITS', lsb_bits])
+ self.putp(ss_byte, es_byte, [cmd, d])
- self.putb([bin_class, bytes([d])])
+ self.putb(ss_byte, es_byte, [bin_class, bytes([d])])
- for b, ss, es in self.data_bits:
+ for bit_value, ss_bit, es_bit in lsb_bits:
cls, texts = proto['BIT'][0], proto['BIT'][1:]
- texts = [t.format(b = b) for t in texts]
- self.put(ss, es, self.out_ann, [cls, texts])
-
- if cmd.startswith('ADDRESS') and is_seven:
- self.ss, self.es = self.samplenum, self.samplenum + self.bitwidth
+ texts = [t.format(b = bit_value) for t in texts]
+ self.putg(ss_bit, es_bit, cls, texts)
+
+ if is_address and has_rw_bit:
+ # Assign the last bit's location to the R/W annotation.
+ # Adjust the address value's location to the left.
+ ss_bit, es_bit = self.data_bits[-1][1], self.data_bits[-1][2]
+ es_byte = self.data_bits[-2][2]
cls = proto[cmd][0]
w = ['Write', 'Wr', 'W'] if self.is_write else ['Read', 'Rd', 'R']
- self.putx([cls, w])
- self.ss, self.es = self.ss_byte, self.samplenum
+ self.putg(ss_bit, es_bit, cls, w)
cls, texts = proto[cmd][0], proto[cmd][1:]
texts = [t.format(b = d) for t in texts]
- self.putx([cls, texts])
+ self.putg(ss_byte, es_byte, cls, texts)
- # Done with this packet.
- self.data_bits.clear()
- self.state = 'FIND ACK'
-
- def get_ack(self, pins):
- scl, sda = pins
- # NOTE! Re-uses the last data bit's width for ACK/NAK as well.
- # Which might be acceptable because this decoder implementation
- # only gets to handle ACK/NAK after all DATA BITS were seen.
- self.ss, self.es = self.samplenum, self.samplenum + self.bitwidth
- cmd = 'NACK' if (sda == 1) else 'ACK'
- self.putp([cmd, None])
+ def get_ack(self, ss, es, value):
+ ss_bit, es_bit = ss, es
+ cmd = 'ACK' if value == 0 else 'NACK'
+ self.putp(ss_bit, es_bit, [cmd, None])
cls, texts = proto[cmd][0], proto[cmd][1:]
- self.putx([cls, texts])
+ self.putg(ss_bit, es_bit, cls, texts)
# Slave addresses can span one or two bytes, before data bytes
# follow. There can be an arbitrary number of data bytes. Stick
# with getting more address bytes if applicable, or enter or
# remain in the data phase of the transfer otherwise.
if self.rem_addr_bytes:
self.rem_addr_bytes -= 1
- if self.rem_addr_bytes:
- self.state = 'FIND ADDRESS'
- else:
- self.state = 'FIND DATA'
+ self.data_bits.clear()
- def handle_stop(self, pins):
+ def handle_stop(self, ss, es):
# Meta bitrate
if self.samplerate and self.pdu_start:
- elapsed = self.samplenum - self.pdu_start + 1
+ elapsed = es - self.pdu_start + 1
elapsed /= self.samplerate
bitrate = int(1 / elapsed * self.pdu_bits)
- ss, es = self.pdu_start, self.samplenum
- self.put(ss, es, self.out_bitrate, bitrate)
+ ss_meta, es_meta = self.pdu_start, es
+ self.put(ss_meta, es_meta, self.out_bitrate, bitrate)
self.pdu_start = None
self.pdu_bits = 0
cmd = 'STOP'
- self.ss, self.es = self.samplenum, self.samplenum
- self.putp([cmd, None])
+ self.putp(ss, es, [cmd, None])
cls, texts = proto[cmd][0], proto[cmd][1:]
- self.putx([cls, texts])
- self.state = 'FIND START'
+ self.putg(ss, es, cls, texts)
self.is_repeat_start = False
self.is_write = None
self.data_bits.clear()
def decode(self):
+ # Check for several bus conditions. Determine sample numbers
+ # here and pass ss, es, and bit values to handling routines.
while True:
# State machine.
- if self.state == 'FIND START':
+ # BEWARE! This implementation expects to see valid traffic,
+ # is rather picky in which phase which symbols get handled.
+ # This attempts to support severely undersampled captures,
+ # which a previous implementation happened to read instead
+ # of rejecting the inadequate input data.
+ # NOTE that handling bits at the start of their validity,
+ # and assuming that they remain valid until the next bit
+ # starts, is also done for backwards compatibility.
+ if self._wants_start():
# Wait for a START condition (S): SCL = high, SDA = falling.
- self.handle_start(self.wait({0: 'h', 1: 'f'}))
- elif self.state == 'FIND ADDRESS':
+ pins = self.wait({0: 'h', 1: 'f'})
+ ss, es = self.samplenum, self.samplenum
+ self.handle_start(ss, es)
+ elif self._collects_address() and self._collects_byte():
# Wait for a data bit: SCL = rising.
- self.handle_address_or_data(self.wait({0: 'r'}))
- elif self.state == 'FIND DATA':
+ pins = self.wait({0: 'r'})
+ _, sda = pins
+ ss, es = self.samplenum, self.samplenum + self.bitwidth
+ self.handle_address_or_data(ss, es, sda)
+ elif self._collects_byte():
# Wait for any of the following conditions (or combinations):
# a) Data sampling of receiver: SCL = rising, and/or
# b) START condition (S): SCL = high, SDA = falling, and/or
# Check which of the condition(s) matched and handle them.
if self.matched[0]:
- self.handle_address_or_data(pins)
+ _, sda = pins
+ ss, es = self.samplenum, self.samplenum + self.bitwidth
+ self.handle_address_or_data(ss, es, sda)
elif self.matched[1]:
- self.handle_start(pins)
+ ss, es = self.samplenum, self.samplenum
+ self.handle_start(ss, es)
elif self.matched[2]:
- self.handle_stop(pins)
- elif self.state == 'FIND ACK':
+ ss, es = self.samplenum, self.samplenum
+ self.handle_stop(ss, es)
+ else:
# Wait for a data/ack bit: SCL = rising.
- self.get_ack(self.wait({0: 'r'}))
+ pins = self.wait({0: 'r'})
+ _, sda = pins
+ ss, es = self.samplenum, self.samplenum + self.bitwidth
+ self.get_ack(ss, es, sda)
projects / libsigrokdecode.git / blobdiff