+# States
+FIND_START = 0
+FIND_ADDRESS = 1
+FIND_DATA = 2
+
+class Decoder(srd.Decoder):
+ id = 'i2c'
+ name = 'I2C'
+ longname = 'Inter-Integrated Circuit'
+ desc = 'I2C is a two-wire, multi-master, serial bus.'
+ longdesc = '...'
+ author = 'Uwe Hermann'
+ email = 'uwe@hermann-uwe.de'
+ license = 'gplv2+'
+ inputs = ['logic']
+ outputs = ['i2c']
+ probes = [
+ {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'},
+ {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
+ ]
+ options = {
+ 'address-space': ['Address space (in bits)', 7],
+ }
+ annotations = [
+ # ANN_SHIFTED
+ ['7-bit shifted hex',
+ 'Read/write bit shifted out from the 8-bit I2C slave address'],
+ # ANN_SHIFTED_SHORT
+ ['7-bit shifted hex (short)',
+ 'Read/write bit shifted out from the 8-bit I2C slave address'],
+ # ANN_RAW
+ ['Raw hex', 'Unaltered raw data'],
+ ]
+
+ def __init__(self, **kwargs):
+ self.samplecnt = 0
+ self.bitcount = 0
+ self.databyte = 0
+ self.wr = -1
+ self.startsample = -1
+ self.is_repeat_start = 0
+ self.state = FIND_START
+ self.oldscl = None
+ self.oldsda = None
+
+ def start(self, metadata):
+ self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2c')
+ self.out_ann = self.add(srd.OUTPUT_ANN, 'i2c')
+
+ def report(self):
+ pass
+
+ def is_start_condition(self, scl, sda):
+ # START condition (S): SDA = falling, SCL = high
+ if (self.oldsda == 1 and sda == 0) and scl == 1:
+ return True
+ return False
+
+ def is_data_bit(self, scl, sda):
+ # Data sampling of receiver: SCL = rising
+ if self.oldscl == 0 and scl == 1:
+ return True
+ return False
+
+ def is_stop_condition(self, scl, sda):
+ # STOP condition (P): SDA = rising, SCL = high
+ if (self.oldsda == 0 and sda == 1) and scl == 1:
+ return True
+ return False
+
+ def found_start(self, scl, sda):
+ cmd = 'START_REPEAT' if (self.is_repeat_start == 1) else 'START'
+
+ self.put(self.out_proto, [cmd, None, None])
+ self.put(self.out_ann, [ANN_SHIFTED, [protocol[cmd][0]]])
+ self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol[cmd][1]]])
+
+ self.state = FIND_ADDRESS
+ self.bitcount = self.databyte = 0
+ self.is_repeat_start = 1
+ self.wr = -1
+
+ def found_address_or_data(self, scl, sda):
+ # Gather 8 bits of data plus the ACK/NACK bit.
+
+ if self.startsample == -1:
+ # TODO: Should be samplenum, as received from the feed.
+ self.startsample = self.samplecnt
+ self.bitcount += 1
+
+ # Address and data are transmitted MSB-first.
+ self.databyte <<= 1
+ self.databyte |= sda
+
+ # Return if we haven't collected all 8 + 1 bits, yet.
+ if self.bitcount != 9:
+ return
+
+ # Send raw output annotation before we start shifting out
+ # read/write and ack/nack bits.
+ self.put(self.out_ann, [ANN_RAW, ['0x%.2x' % self.databyte]])
+
+ # We received 8 address/data bits and the ACK/NACK bit.
+ self.databyte >>= 1 # Shift out unwanted ACK/NACK bit here.
+
+ if self.state == FIND_ADDRESS:
+ # The READ/WRITE bit is only in address bytes, not data bytes.
+ self.wr = 0 if (self.databyte & 1) else 1
+ d = self.databyte >> 1
+ elif self.state == FIND_DATA:
+ d = self.databyte
+ else:
+ # TODO: Error?
+ pass
+
+ # Last bit that came in was the ACK/NACK bit (1 = NACK).
+ ack_bit = 'NACK' if (sda == 1) else 'ACK'
+
+ if self.state == FIND_ADDRESS and self.wr == 1:
+ cmd = 'ADDRESS_WRITE'
+ elif self.state == FIND_ADDRESS and self.wr == 0:
+ cmd = 'ADDRESS_READ'
+ elif self.state == FIND_DATA and self.wr == 1:
+ cmd = 'DATA_WRITE'
+ elif self.state == FIND_DATA and self.wr == 0:
+ cmd = 'DATA_READ'
+
+ self.put(self.out_proto, [cmd, d, ack_bit])
+ self.put(self.out_ann, [ANN_SHIFTED,
+ [protocol[cmd][0], '0x%02x' % d, protocol[ack_bit][0]]])
+ self.put(self.out_ann, [ANN_SHIFTED_SHORT,
+ [protocol[cmd][1], '0x%02x' % d, protocol[ack_bit][1]]])
+
+ self.bitcount = self.databyte = 0
+ self.startsample = -1
+
+ if self.state == FIND_ADDRESS:
+ self.state = FIND_DATA
+ elif self.state == FIND_DATA:
+ # There could be multiple data bytes in a row.
+ # So, either find a STOP condition or another data byte next.
+ pass
+
+ def found_stop(self, scl, sda):
+ self.put(self.out_proto, ['STOP', None, None])
+ self.put(self.out_ann, [ANN_SHIFTED, [protocol['STOP'][0]]])
+ self.put(self.out_ann, [ANN_SHIFTED_SHORT, [protocol['STOP'][1]]])
+
+ self.state = FIND_START
+ self.is_repeat_start = 0
+ self.wr = -1
+
+ def put(self, output_id, data):
+ # Inject sample range into the call up to sigrok.
+ # TODO: 0-0 sample range for now.
+ super(Decoder, self).put(0, 0, output_id, data)
+
+ def decode(self, timeoffset, duration, data):
+ for samplenum, (scl, sda) in data:
+ self.samplecnt += 1
+
+ # First sample: Save SCL/SDA value.
+ if self.oldscl == None:
+ self.oldscl = scl
+ self.oldsda = sda
+ continue
+
+ # TODO: Wait until the bus is idle (SDA = SCL = 1) first?
+
+ # State machine.
+ if self.state == FIND_START:
+ if self.is_start_condition(scl, sda):
+ self.found_start(scl, sda)
+ elif self.state == FIND_ADDRESS:
+ if self.is_data_bit(scl, sda):
+ self.found_address_or_data(scl, sda)
+ elif self.state == FIND_DATA:
+ if self.is_data_bit(scl, sda):
+ self.found_address_or_data(scl, sda)
+ elif self.is_start_condition(scl, sda):
+ self.found_start(scl, sda)
+ elif self.is_stop_condition(scl, sda):
+ self.found_stop(scl, sda)
+ else:
+ # TODO: Error?
+ pass
+
+ # Save current SDA/SCL values for the next round.
+ self.oldscl = scl
+ self.oldsda = sda