license: remove FSF postal address from boiler plate license text

[libsigrokdecode.git] / decoders / em4100 / pd.py

diff --git a/decoders/em4100/pd.py b/decoders/em4100/pd.py
index d9b62a50fddf00ce6c5d3e8c2d88950b2de221e1..faba51b773e54e1d24390649c49ff22c301bbf1f 100644 (file)
--- a/decoders/em4100/pd.py
+++ b/decoders/em4100/pd.py
@@ -5,8 +5,8 @@
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either data 2 of the License, or
-## (at your option) any later data.
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
 ##
 ## This program is distributed in the hope that it will be useful,
 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -14,8 +14,7 @@
 ## GNU General Public License for more details.
 ##
 ## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## along with this program; if not, see <http://www.gnu.org/licenses/>.
 ##
 
 import sigrokdecode as srd
@@ -62,7 +61,7 @@ class Decoder(srd.Decoder):
         ('tags', 'Tags', (9,)),
     )
 
-    def __init__(self, **kwargs):
+    def __init__(self):
         self.samplerate = None
         self.oldpin = None
         self.last_samplenum = None
@@ -74,12 +73,12 @@ class Decoder(srd.Decoder):
         self.oldpl = 0
         self.oldsamplenum = 0
         self.last_bit_pos = 0
-        self.first_ss = 0
+        self.ss_first = 0
         self.first_one = 0
         self.state = 'HEADER'
         self.data = 0
         self.data_bits = 0
-        self.data_ss = 0
+        self.ss_data = 0
         self.data_parity = 0
         self.payload_cnt = 0
         self.data_col_parity = [0, 0, 0, 0, 0, 0]
@@ -98,20 +97,21 @@ class Decoder(srd.Decoder):
     def start(self):
         self.out_ann = self.register(srd.OUTPUT_ANN)
 
-    def add_bit(self, bit, ss, es):
+    def putbit(self, bit, ss, es):
+        self.put(ss, es, self.out_ann, [0, [str(bit)]])
         if self.state == 'HEADER':
             if bit == 1:
                 if self.first_one > 0:
                     self.first_one += 1
                 if self.first_one == 9:
-                    self.put(self.first_ss, es, self.out_ann,
+                    self.put(self.ss_first, es, self.out_ann,
                              [1, ['Header', 'Head', 'He', 'H']])
                     self.first_one = 0
                     self.state = 'PAYLOAD'
                     return
                 if self.first_one == 0:
                     self.first_one = 1
-                    self.first_ss = ss
+                    self.ss_first = ss
 
             if bit == 0:
                 self.first_one = 0
@@ -120,14 +120,14 @@ class Decoder(srd.Decoder):
         if self.state == 'PAYLOAD':
             self.payload_cnt += 1
             if self.data_bits == 0:
-                self.data_ss = ss
+                self.ss_data = ss
                 self.data = 0
                 self.data_parity = 0
             self.data_bits += 1
             if self.data_bits == 5:
                 s = 'Version/customer' if self.payload_cnt <= 10 else 'Data'
                 c = 2 if self.payload_cnt <= 10 else 3
-                self.put(self.data_ss, ss, self.out_ann,
+                self.put(self.ss_data, ss, self.out_ann,
                          [c, [s + ': %X' % self.data, '%X' % self.data]])
                 s = 'OK' if self.data_parity == bit else 'ERROR'
                 c = 4 if s == 'OK' else 5
@@ -149,7 +149,7 @@ class Decoder(srd.Decoder):
         if self.state == 'TRAILER':
             self.payload_cnt += 1
             if self.data_bits == 0:
-                self.data_ss = ss
+                self.ss_data = ss
                 self.data = 0
                 self.data_parity = 0
             self.data_bits += 1
@@ -171,7 +171,7 @@ class Decoder(srd.Decoder):
                 # Emit an annotation for valid-looking tags.
                 all_col_parity_ok = (self.data_col_parity[1:5] == self.col_parity[1:5])
                 if all_col_parity_ok and self.all_row_parity_ok:
-                    self.put(self.first_ss, es, self.out_ann,
+                    self.put(self.ss_first, es, self.out_ann,
                              [9, ['Tag: %010X' % self.tag, 'Tag', 'T']])
 
                 self.tag = 0
@@ -185,40 +185,25 @@ class Decoder(srd.Decoder):
                     self.col_parity_pos = []
                     self.all_row_parity_ok = True
 
-    def putbit(self, bit, ss, es):
-        self.put(ss, es, self.out_ann, [0, [str(bit)]])
-        self.add_bit(bit, ss, es)
-
     def manchester_decode(self, samplenum, pl, pp, pin):
-        ss, es = 0, 0
         bit = self.oldpin ^ self.polarity
         if pl > self.halfbit_limit:
-            samples = samplenum - self.oldsamplenum
-            t = samples / self.samplerate
-
+            es = int(samplenum - pl/2)
             if self.oldpl > self.halfbit_limit:
                 ss = int(self.oldsamplenum - self.oldpl/2)
-                es = int(samplenum - pl/2)
-                self.putbit(bit, ss, es)
-            if self.oldpl <= self.halfbit_limit:
+            else:
                 ss = int(self.oldsamplenum - self.oldpl)
-                es = int(samplenum - pl/2)
-                self.putbit(bit, ss, es)
+            self.putbit(bit, ss, es)
             self.last_bit_pos = int(samplenum - pl/2)
-
-        if pl < self.halfbit_limit:
-            samples = samplenum - self.oldsamplenum
-            t = samples / self.samplerate
-
+        else:
+            es = int(samplenum)
             if self.oldpl > self.halfbit_limit:
                 ss = int(self.oldsamplenum - self.oldpl/2)
-                es = int(samplenum)
                 self.putbit(bit, ss, es)
                 self.last_bit_pos = int(samplenum)
-            if self.oldpl <= self.halfbit_limit:
+            else:
                 if self.last_bit_pos <= self.oldsamplenum - self.oldpl:
                     ss = int(self.oldsamplenum - self.oldpl)
-                    es = int(samplenum)
                     self.putbit(bit, ss, es)
                     self.last_bit_pos = int(samplenum)
 
@@ -244,9 +229,7 @@ class Decoder(srd.Decoder):
             if self.oldpin != pin:
                 pl = samplenum - self.oldsamplenum
                 pp = pin
-
                 self.manchester_decode(samplenum, pl, pp, pin)
-
                 self.oldpl = pl
                 self.oldpp = pp
                 self.oldsamplenum = samplenum