avr_isp: Add more parts

[libsigrokdecode.git] / decoders / dsi / pd.py

diff --git a/decoders/dsi/pd.py b/decoders/dsi/pd.py
index 7be29c3386cd49fb5921cc70706c60d14bbed290..b5faf6f699b0ed111e87547db9551b135a641398 100644 (file)
--- a/decoders/dsi/pd.py
+++ b/decoders/dsi/pd.py
@@ -30,7 +30,7 @@ class Decoder(srd.Decoder):
     desc = 'Digital Serial Interface (DSI) lighting protocol.'
     license = 'gplv2+'
     inputs = ['logic']
-    outputs = ['dsi']
+    outputs = []
     tags = ['Embedded/industrial', 'Lighting']
     channels = (
         {'id': 'dsi', 'name': 'DSI', 'desc': 'DSI data line'},
@@ -47,7 +47,7 @@ class Decoder(srd.Decoder):
     )
     annotation_rows = (
         ('bits', 'Bits', (0,)),
-        ('raw', 'Raw data', (3,)),
+        ('raw-vals', 'Raw data', (3,)),
         ('fields', 'Fields', (1, 2)),
     )
 
@@ -56,7 +56,6 @@ class Decoder(srd.Decoder):
 
     def reset(self):
         self.samplerate = None
-        self.samplenum = None
         self.edges, self.bits, self.ss_es_bits = [], [], []
         self.state = 'IDLE'
 
@@ -112,6 +111,7 @@ class Decoder(srd.Decoder):
             raise SamplerateError('Cannot decode without samplerate.')
         bit = 0
         while True:
+            # TODO: Come up with more appropriate self.wait() conditions.
             (self.dsi,) = self.wait()
             if self.options['polarity'] == 'active-high':
                 self.dsi ^= 1 # Invert.