ds1307: Consistently use _ instead of - for various IDs.

[libsigrokdecode.git] / decoders / ds1307 / pd.py

diff --git a/decoders/ds1307/pd.py b/decoders/ds1307/pd.py
index ca6faf6c92c9ea199912dce2e95f9fa6878813fd..920f12586eb42170aa2f057d38f3dee13a54ca61 100644 (file)
--- a/decoders/ds1307/pd.py
+++ b/decoders/ds1307/pd.py
@@ -15,12 +15,12 @@
 ## GNU General Public License for more details.
 ##
 ## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## along with this program; if not, see <http://www.gnu.org/licenses/>.
 ##
 
 import re
 import sigrokdecode as srd
+from common.srdhelper import bcd2int
 
 days_of_week = (
     'Sunday', 'Monday', 'Tuesday', 'Wednesday',
@@ -39,42 +39,46 @@ bits = (
 
 rates = {
     0b00: '1Hz',
-    0b01: '4096kHz',
-    0b10: '8192kHz',
-    0b11: '32768kHz',
+    0b01: '4096Hz',
+    0b10: '8192Hz',
+    0b11: '32768Hz',
 }
 
+DS1307_I2C_ADDRESS = 0x68
+
 def regs_and_bits():
-    l = [('reg-' + r.lower(), r + ' register') for r in regs]
-    l += [('bit-' + re.sub('\/| ', '-', b).lower(), b + ' bit') for b in bits]
+    l = [('reg_' + r.lower(), r + ' register') for r in regs]
+    l += [('bit_' + re.sub('\/| ', '_', b).lower(), b + ' bit') for b in bits]
     return tuple(l)
 
-# Return the specified BCD number (max. 8 bits) as integer.
-def bcd2int(b):
-    return (b & 0x0f) + ((b >> 4) * 10)
-
 class Decoder(srd.Decoder):
-    api_version = 2
+    api_version = 3
     id = 'ds1307'
     name = 'DS1307'
     longname = 'Dallas DS1307'
-    desc = 'Realtime clock module protocol.'
+    desc = 'Dallas DS1307 realtime clock module protocol.'
     license = 'gplv2+'
     inputs = ['i2c']
-    outputs = ['ds1307']
+    outputs = []
+    tags = ['Clock/timing', 'IC']
     annotations =  regs_and_bits() + (
-        ('read-datetime', 'Read date/time'),
-        ('write-datetime', 'Write date/time'),
-        ('reg-read', 'Register read'),
-        ('reg-write', 'Register write'),
+        ('read_date_time', 'Read date/time'),
+        ('write_date_time', 'Write date/time'),
+        ('reg_read', 'Register read'),
+        ('reg_write', 'Register write'),
+        ('warning', 'Warning'),
     )
     annotation_rows = (
         ('bits', 'Bits', tuple(range(9, 24))),
         ('regs', 'Registers', tuple(range(9))),
-        ('date-time', 'Date/time', (24, 25, 26, 27)),
+        ('date_time', 'Date/time', (24, 25, 26, 27)),
+        ('warnings', 'Warnings', (28,)),
     )
 
-    def __init__(self, **kwargs):
+    def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.state = 'IDLE'
         self.hours = -1
         self.minutes = -1
@@ -118,7 +122,7 @@ class Decoder(srd.Decoder):
         ampm_mode = True if (b & (1 << 6)) else False
         if ampm_mode:
             self.putd(6, 6, [13, ['12-hour mode', '12h mode', '12h']])
-            a = 'AM' if (b & (1 << 6)) else 'PM'
+            a = 'PM' if (b & (1 << 5)) else 'AM'
             self.putd(5, 5, [14, [a, a[0]]])
             h = self.hours = bcd2int(b & 0x1f)
             self.putd(4, 0, [15, ['Hour: %d' % h, 'H: %d' % h, 'H']])
@@ -180,7 +184,7 @@ class Decoder(srd.Decoder):
         d = '%s, %02d.%02d.%4d %02d:%02d:%02d' % (
             days_of_week[self.days - 1], self.date, self.months,
             self.years, self.hours, self.minutes, self.seconds)
-        self.put(self.block_start_sample, self.es, self.out_ann,
+        self.put(self.ss_block, self.es, self.out_ann,
                  [cls, ['%s date/time: %s' % (rw, d)]])
 
     def handle_reg(self, b):
@@ -193,6 +197,13 @@ class Decoder(srd.Decoder):
         if self.reg > 0x3f:
             self.reg = 0
 
+    def is_correct_chip(self, addr):
+        if addr == DS1307_I2C_ADDRESS:
+            return True
+        self.put(self.ss_block, self.es, self.out_ann,
+                 [28, ['Ignoring non-DS1307 data (slave 0x%02X)' % addr]])
+        return False
+
     def decode(self, ss, es, data):
         cmd, databyte = data
 
@@ -211,12 +222,14 @@ class Decoder(srd.Decoder):
             if cmd != 'START':
                 return
             self.state = 'GET SLAVE ADDR'
-            self.block_start_sample = ss
+            self.ss_block = ss
         elif self.state == 'GET SLAVE ADDR':
             # Wait for an address write operation.
-            # TODO: We should only handle packets to the RTC slave (0x68).
             if cmd != 'ADDRESS WRITE':
                 return
+            if not self.is_correct_chip(databyte):
+                self.state = 'IDLE'
+                return
             self.state = 'GET REG ADDR'
         elif self.state == 'GET REG ADDR':
             # Wait for a data write (master selects the slave register).
@@ -237,10 +250,12 @@ class Decoder(srd.Decoder):
                 self.state = 'IDLE'
         elif self.state == 'READ RTC REGS':
             # Wait for an address read operation.
-            # TODO: We should only handle packets to the RTC slave (0x68).
-            if cmd == 'ADDRESS READ':
-                self.state = 'READ RTC REGS2'
+            if cmd != 'ADDRESS READ':
+                return
+            if not self.is_correct_chip(databyte):
+                self.state = 'IDLE'
                 return
+            self.state = 'READ RTC REGS2'
         elif self.state == 'READ RTC REGS2':
             if cmd == 'DATA READ':
                 self.handle_reg(databyte)