dcf77: annotate unexpected bit numbers and values, do not abort execution

[libsigrokdecode.git] / decoders / dcf77 / pd.py

diff --git a/decoders/dcf77/pd.py b/decoders/dcf77/pd.py
index b643631081b7e1babed940146b8f87f5aa0136bb..7b09ce6ab9968f15de09ace7823df0a1e0c4ccd8 100644 (file)
--- a/decoders/dcf77/pd.py
+++ b/decoders/dcf77/pd.py
@@ -65,6 +65,9 @@ class Decoder(srd.Decoder):
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.samplerate = None
         self.state = 'WAIT FOR RISING EDGE'
         self.ss_bit = self.ss_bit_old = self.es_bit = self.ss_block = 0
@@ -75,9 +78,6 @@ class Decoder(srd.Decoder):
     def start(self):
         self.out_ann = self.register(srd.OUTPUT_ANN)
 
-        # Assume that the initial pin state is logic 1.
-        self.initial_pins = [1]
-
     def metadata(self, key, value):
         if key == srd.SRD_CONF_SAMPLERATE:
             self.samplerate = value
@@ -127,7 +127,7 @@ class Decoder(srd.Decoder):
             else:
                 self.tmp |= (bit << (c - 1))
             if c == 14:
-                s = bin(self.tmp)[2:].zfill(14)
+                s = '{:014b}'.format(self.tmp)
                 self.putb([1, ['Special bits: %s' % s, 'SB: %s' % s]])
         elif c == 15:
             s = '' if (bit == 1) else 'not '
@@ -210,9 +210,13 @@ class Decoder(srd.Decoder):
                 self.tmp |= (bit << (c - 42))
             if c == 44:
                 d = bcd2int(self.tmp)
-                dn = calendar.day_name[d - 1] # day_name[0] == Monday
-                self.putb([13, ['Day of week: %d (%s)' % (d, dn),
-                                'DoW: %d (%s)' % (d, dn)]])
+                try:
+                    dn = calendar.day_name[d - 1] # day_name[0] == Monday
+                    self.putb([13, ['Day of week: %d (%s)' % (d, dn),
+                                    'DoW: %d (%s)' % (d, dn)]])
+                except IndexError:
+                    self.putb([19, ['Day of week: %d (%s)' % (d, 'invalid'),
+                                    'DoW: %d (%s)' % (d, 'inv')]])
         elif c in range(45, 49 + 1):
             # Month (1-12): DCF77 bits 45-49 (BCD format).
             if c == 45:
@@ -222,9 +226,13 @@ class Decoder(srd.Decoder):
                 self.tmp |= (bit << (c - 45))
             if c == 49:
                 m = bcd2int(self.tmp)
-                mn = calendar.month_name[m] # month_name[1] == January
-                self.putb([14, ['Month: %d (%s)' % (m, mn),
-                                'Mon: %d (%s)' % (m, mn)]])
+                try:
+                    mn = calendar.month_name[m] # month_name[1] == January
+                    self.putb([14, ['Month: %d (%s)' % (m, mn),
+                                    'Mon: %d (%s)' % (m, mn)]])
+                except IndexError:
+                    self.putb([19, ['Month: %d (%s)' % (m, 'invalid'),
+                                    'Mon: %d (%s)' % (m, 'inv')]])
         elif c in range(50, 57 + 1):
             # Year (0-99): DCF77 bits 50-57 (BCD format).
             if c == 50:
@@ -241,7 +249,8 @@ class Decoder(srd.Decoder):
             self.putx([16, ['Date parity: %s' % s, 'DP: %s' % s]])
             self.datebits = []
         else:
-            raise Exception('Invalid DCF77 bit: %d' % c)
+            self.putx([19, ['Invalid DCF77 bit: %d' % c,
+                            'Invalid bit: %d' % c, 'Inv: %d' % c]])
 
     def decode(self):
         if not self.samplerate:
@@ -290,11 +299,12 @@ class Decoder(srd.Decoder):
                 elif len_high_ms in range(161, 260 + 1):
                     bit = 1
                 else:
-                    bit = -1 # TODO: Error?
+                    bit = -1
 
-                # There's no bit 59, make sure none is decoded.
-                if bit in (0, 1) and self.bitcount in range(0, 58 + 1):
+                if bit in (0, 1):
                     self.handle_dcf77_bit(bit)
                     self.bitcount += 1
+                else:
+                    self.putx([19, ['Invalid bit timing', 'Inv timing', 'Inv']])
 
                 self.state = 'WAIT FOR RISING EDGE'