## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2012-2015 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2019 Zhiyuan Wan <dv.xw@qq.com>
+## Copyright (C) 2019 Kongou Hikari <hikari@iloli.bid>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
'SHIFT-IR', 'EXIT1-IR', 'EXIT2-IR',
]
+cjtag_states = [
+ 'CJTAG-EC', 'CJTAG-SPARE', 'CJTAG-TPDEL', 'CJTAG-TPREV', 'CJTAG-TPST',
+ 'CJTAG-RDYC', 'CJTAG-DLYC', 'CJTAG-SCNFMT', 'CJTAG-CP', 'CJTAG-OAC',
+ 'OSCAN1', '4-WIRE',
+]
+
class Decoder(srd.Decoder):
api_version = 3
- id = 'jtag'
- name = 'JTAG'
- longname = 'Joint Test Action Group (IEEE 1149.1)'
+ id = 'cjtag'
+ name = 'cJTAG'
+ longname = 'Compact Joint Test Action Group (IEEE 1149.7)'
desc = 'Protocol for testing, debugging, and flashing ICs.'
license = 'gplv2+'
inputs = ['logic']
outputs = ['jtag']
tags = ['Debug/trace']
channels = (
- {'id': 'tdi', 'name': 'TDI', 'desc': 'Test data input'},
- {'id': 'tdo', 'name': 'TDO', 'desc': 'Test data output'},
- {'id': 'tck', 'name': 'TCK', 'desc': 'Test clock'},
- {'id': 'tms', 'name': 'TMS', 'desc': 'Test mode select'},
- )
- optional_channels = (
- {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'},
- {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'},
- {'id': 'rtck', 'name': 'RTCK', 'desc': 'Return clock signal'},
+ {'id': 'tckc', 'name': 'TCKC', 'desc': 'Test clock'},
+ {'id': 'tmsc', 'name': 'TMSC', 'desc': 'Test mode select'},
)
- annotations = tuple([tuple([s.lower(), s]) for s in jtag_states]) + ( \
+ annotations = \
+ tuple([tuple([s.lower(), s]) for s in jtag_states]) + \
+ tuple([tuple([s.lower(), s]) for s in cjtag_states]) + ( \
('bit-tdi', 'Bit (TDI)'),
('bit-tdo', 'Bit (TDO)'),
('bitstring-tdi', 'Bitstring (TDI)'),
('bitstring-tdo', 'Bitstring (TDO)'),
+ ('bit-tms', 'Bit (TMS)'),
)
annotation_rows = (
- ('bits-tdi', 'Bits (TDI)', (16,)),
- ('bits-tdo', 'Bits (TDO)', (17,)),
- ('bitstrings-tdi', 'Bitstrings (TDI)', (18,)),
- ('bitstrings-tdo', 'Bitstrings (TDO)', (19,)),
- ('states', 'States', tuple(range(15 + 1))),
+ ('bits-tdi', 'Bits (TDI)', (28,)),
+ ('bits-tdo', 'Bits (TDO)', (29,)),
+ ('bitstrings-tdi', 'Bitstrings (TDI)', (30,)),
+ ('bitstrings-tdo', 'Bitstrings (TDO)', (31,)),
+ ('bits-tms', 'Bits (TMS)', (32,)),
+ ('cjtag-states', 'CJTAG states',
+ tuple(range(len(jtag_states), len(jtag_states + cjtag_states)))),
+ ('jtag-states', 'JTAG states', tuple(range(len(jtag_states)))),
)
def __init__(self):
def reset(self):
# self.state = 'TEST-LOGIC-RESET'
self.state = 'RUN-TEST/IDLE'
+ self.cjtagstate = '4-WIRE'
+ self.oldcjtagstate = None
+ self.escape_edges = 0
+ self.oaclen = 0
+ self.oldtms = 0
+ self.oacp = 0
+ self.oscan1cycle = 0
self.oldstate = None
self.bits_tdi = []
self.bits_tdo = []
def advance_state_machine(self, tms):
self.oldstate = self.state
+ if self.cjtagstate.startswith('CJTAG-'):
+ self.oacp += 1
+ if self.oacp > 4 and self.oaclen == 12:
+ self.cjtagstate = 'CJTAG-EC'
+
+ if self.oacp == 8 and tms == 0:
+ self.oaclen = 36
+ if self.oacp > 8 and self.oaclen == 36:
+ self.cjtagstate = 'CJTAG-SPARE'
+ if self.oacp > 13 and self.oaclen == 36:
+ self.cjtagstate = 'CJTAG-TPDEL'
+ if self.oacp > 16 and self.oaclen == 36:
+ self.cjtagstate = 'CJTAG-TPREV'
+ if self.oacp > 18 and self.oaclen == 36:
+ self.cjtagstate = 'CJTAG-TPST'
+ if self.oacp > 23 and self.oaclen == 36:
+ self.cjtagstate = 'CJTAG-RDYC'
+ if self.oacp > 25 and self.oaclen == 36:
+ self.cjtagstate = 'CJTAG-DLYC'
+ if self.oacp > 27 and self.oaclen == 36:
+ self.cjtagstate = 'CJTAG-SCNFMT'
+
+ if self.oacp > 8 and self.oaclen == 12:
+ self.cjtagstate = 'CJTAG-CP'
+ if self.oacp > 32 and self.oaclen == 36:
+ self.cjtagstate = 'CJTAG-CP'
+
+ if self.oacp > self.oaclen:
+ self.cjtagstate = 'OSCAN1'
+ self.oscan1cycle = 1
+ # Because Nuclei cJTAG device asserts a reset during cJTAG
+ # online activating.
+ self.state = 'TEST-LOGIC-RESET'
+ return
+
# Intro "tree"
if self.state == 'TEST-LOGIC-RESET':
self.state = 'TEST-LOGIC-RESET' if (tms) else 'RUN-TEST/IDLE'
elif self.state == 'UPDATE-IR':
self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
- def handle_rising_tck_edge(self, pins):
- (tdi, tdo, tck, tms, trst, srst, rtck) = pins
+ def handle_rising_tckc_edge(self, tdi, tdo, tck, tms):
# Rising TCK edges always advance the state machine.
self.advance_state_machine(tms)
self.putx([jtag_states.index(self.oldstate), [self.oldstate]])
self.putp(['NEW STATE', self.state])
+ self.putx([len(jtag_states) + cjtag_states.index(self.oldcjtagstate),
+ [self.oldcjtagstate]])
+ if (self.oldcjtagstate.startswith('CJTAG-')):
+ self.putx([32, [str(self.oldtms)]])
+ self.oldtms = tms
+
# Upon SHIFT-*/EXIT1-* collect the current TDI/TDO values.
if self.oldstate.startswith('SHIFT-') or \
self.oldstate.startswith('EXIT1-'):
self.ss_bitstring = self.samplenum
self.first_bit = False
else:
- self.putx([16, [str(self.bits_tdi[0])]])
- self.putx([17, [str(self.bits_tdo[0])]])
+ self.putx([28, [str(self.bits_tdi[0])]])
+ self.putx([29, [str(self.bits_tdo[0])]])
# Use self.samplenum as ES of the previous bit.
self.bits_samplenums_tdi[0][1] = self.samplenum
self.bits_samplenums_tdo[0][1] = self.samplenum
b = ''.join(map(str, self.bits_tdi[1:]))
h = ' (0x%x' % int('0b0' + b, 2) + ')'
s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi[1:])) + ' bits'
- self.putx_bs([18, [s]])
+ self.putx_bs([30, [s]])
self.putp_bs([t, [b, self.bits_samplenums_tdi[1:]]])
self.bits_tdi = []
self.bits_samplenums_tdi = []
b = ''.join(map(str, self.bits_tdo[1:]))
h = ' (0x%x' % int('0b0' + b, 2) + ')'
s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo[1:])) + ' bits'
- self.putx_bs([19, [s]])
+ self.putx_bs([31, [s]])
self.putp_bs([t, [b, self.bits_samplenums_tdo[1:]]])
self.bits_tdo = []
self.bits_samplenums_tdo = []
self.ss_item = self.samplenum
+ def handle_tmsc_edge(self):
+ self.escape_edges += 1
+
+ def handle_tapc_state(self):
+ self.oldcjtagstate = self.cjtagstate
+
+ if self.escape_edges >= 8:
+ self.cjtagstate = '4-WIRE'
+ if self.escape_edges == 6:
+ self.cjtagstate = 'CJTAG-OAC'
+ self.oacp = 0
+ self.oaclen = 12
+
+ self.escape_edges = 0
+
def decode(self):
+ tdi = tms = tdo = 0
+
while True:
- # Wait for a rising edge on TCK.
- self.handle_rising_tck_edge(self.wait({2: 'r'}))
+ # Wait for a rising edge on TCKC.
+ tckc, tmsc = self.wait({0: 'r'})
+ self.handle_tapc_state()
+
+ if self.cjtagstate == 'OSCAN1':
+ if self.oscan1cycle == 0: # nTDI
+ tdi = 1 if (tmsc == 0) else 0
+ self.oscan1cycle = 1
+ elif self.oscan1cycle == 1: # TMS
+ tms = tmsc
+ self.oscan1cycle = 2
+ elif self.oscan1cycle == 2: # TDO
+ tdo = tmsc
+ self.handle_rising_tckc_edge(tdi, tdo, tckc, tms)
+ self.oscan1cycle = 0
+ else:
+ self.handle_rising_tckc_edge(None, None, tckc, tmsc)
+
+ while (tckc == 1):
+ tckc, tmsc_n = self.wait([{0: 'f'}, {1: 'e'}])
+ if tmsc_n != tmsc:
+ tmsc = tmsc_n
+ self.handle_tmsc_edge()
projects / libsigrokdecode.git / blobdiff