## along with this program; if not, see <http://www.gnu.org/licenses/>.
##
+from common.srdhelper import bitpack_msb
import sigrokdecode as srd
class SamplerateError(Exception):
pass
+def dlc2len(dlc):
+ return [0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64][dlc]
+
class Decoder(srd.Decoder):
api_version = 3
id = 'can'
desc = 'Field bus protocol for distributed realtime control.'
license = 'gplv2+'
inputs = ['logic']
- outputs = []
+ outputs = ['can']
tags = ['Automotive']
channels = (
{'id': 'can_rx', 'name': 'CAN RX', 'desc': 'CAN bus line'},
)
options = (
- {'id': 'bitrate', 'desc': 'Bitrate (bits/s)', 'default': 1000000},
+ {'id': 'nominal_bitrate', 'desc': 'Nominal bitrate (bits/s)', 'default': 1000000},
+ {'id': 'fast_bitrate', 'desc': 'Fast bitrate (bits/s)', 'default': 2000000},
{'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 70.0},
)
annotations = (
- ('data', 'CAN payload data'),
+ ('data', 'Payload data'),
('sof', 'Start of frame'),
('eof', 'End of frame'),
('id', 'Identifier'),
('ack-slot', 'ACK slot'),
('ack-delimiter', 'ACK delimiter'),
('stuff-bit', 'Stuff bit'),
- ('warnings', 'Human-readable warnings'),
+ ('warning', 'Warning'),
('bit', 'Bit'),
)
annotation_rows = (
('fields', 'Fields', tuple(range(15))),
('warnings', 'Warnings', (16,)),
)
- fd = False
def __init__(self):
self.reset()
- def dlc2len(self, dlc):
- return [0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64][dlc]
-
def reset(self):
self.samplerate = None
self.reset_variables()
def start(self):
self.out_ann = self.register(srd.OUTPUT_ANN)
+ self.out_python = self.register(srd.OUTPUT_PYTHON)
+
+ def set_bit_rate(self, bitrate):
+ self.bit_width = float(self.samplerate) / float(bitrate)
+ self.sample_point = (self.bit_width / 100.0) * self.options['sample_point']
+
+ def set_nominal_bitrate(self):
+ self.set_bit_rate(self.options['nominal_bitrate'])
+
+ def set_fast_bitrate(self):
+ self.set_bit_rate(self.options['fast_bitrate'])
def metadata(self, key, value):
if key == srd.SRD_CONF_SAMPLERATE:
self.samplerate = value
- self.bit_width = float(self.samplerate) / float(self.options['bitrate'])
+ self.bit_width = float(self.samplerate) / float(self.options['nominal_bitrate'])
self.sample_point = (self.bit_width / 100.0) * self.options['sample_point']
# Generic helper for CAN bit annotations.
def put12(self, data):
self.putg(self.ss_bit12, self.ss_bit12, data)
+ # Single-CAN-bit annotation using the samplenum of CAN bit 32.
+ def put32(self, data):
+ self.putg(self.ss_bit32, self.ss_bit32, data)
+
# Multi-CAN-bit annotation from self.ss_block to current samplenum.
def putb(self, data):
self.putg(self.ss_block, self.samplenum, data)
+ def putpy(self, data):
+ self.put(self.ss_packet, self.es_packet, self.out_python, data)
+
def reset_variables(self):
self.state = 'IDLE'
self.sof = self.frame_type = self.dlc = None
self.last_databit = 999 # Positive value that bitnum+x will never match
self.ss_block = None
self.ss_bit12 = None
+ self.ss_bit32 = None
self.ss_databytebits = []
+ self.frame_bytes = []
+ self.rtr_type = None
+ self.fd = False
+ self.rtr = None
# Poor man's clock synchronization. Use signal edges which change to
# dominant state in rather simple ways. This naive approach is neither
self.dom_edge_snum = self.samplenum
self.dom_edge_bcount = self.curbit
- def bit_sampled(self):
- # EMPTY
- pass
-
# Determine the position of the next desired bit's sample point.
def get_sample_point(self, bitnum):
samplenum = self.dom_edge_snum
- samplenum += int(self.bit_width * (bitnum - self.dom_edge_bcount))
- samplenum += int(self.sample_point)
- return samplenum
+ samplenum += self.bit_width * (bitnum - self.dom_edge_bcount)
+ samplenum += self.sample_point
+ return int(samplenum)
def is_stuff_bit(self):
# CAN uses NRZ encoding and bit stuffing.
# Remember start of CRC sequence (see below).
if bitnum == (self.last_databit + 1):
self.ss_block = self.samplenum
-
if self.fd:
- if self.dlc2len(self.dlc) < 16:
+ if dlc2len(self.dlc) < 16:
self.crc_len = 27 # 17 + SBC + stuff bits
else:
self.crc_len = 32 # 21 + SBC + stuff bits
# CRC sequence (15 bits, 17 bits or 21 bits)
elif bitnum == (self.last_databit + self.crc_len):
if self.fd:
- if self.dlc2len(self.dlc) < 16:
- crc_type = "CRC-17"
- else:
- crc_type = "CRC-21"
+ if dlc2len(self.dlc) < 16:
+ crc_type = "CRC-17"
+ else:
+ crc_type = "CRC-21"
else:
- crc_type = "CRC-15"
+ crc_type = "CRC-15"
x = self.last_databit + 1
crc_bits = self.bits[x:x + self.crc_len + 1]
- self.crc = int(''.join(str(d) for d in crc_bits), 2)
+ self.crc = bitpack_msb(crc_bits)
self.putb([11, ['%s sequence: 0x%04x' % (crc_type, self.crc),
'%s: 0x%04x' % (crc_type, self.crc), '%s' % crc_type]])
if not self.is_valid_crc(crc_bits):
if can_rx != 1:
self.putx([16, ['CRC delimiter must be a recessive bit']])
+ if self.fd:
+ self.set_nominal_bitrate()
+
# ACK slot bit (dominant: ACK, recessive: NACK)
elif bitnum == (self.last_databit + self.crc_len + 2):
ack = 'ACK' if can_rx == 0 else 'NACK'
self.ss_block = self.samplenum
# End of frame (EOF), 7 recessive bits
- elif bitnum == (self.last_databit + self.crc_len + 11):
+ elif bitnum == (self.last_databit + self.crc_len + 10):
self.putb([2, ['End of frame', 'EOF', 'E']])
if self.rawbits[-7:] != [1, 1, 1, 1, 1, 1, 1]:
self.putb([16, ['End of frame (EOF) must be 7 recessive bits']])
+ self.es_packet = self.samplenum
+ py_data = tuple([self.frame_type, self.fullid, self.rtr_type,
+ self.dlc, self.frame_bytes])
+ self.putpy(py_data)
self.reset_variables()
return True
# Returns True if the frame ended (EOF), False otherwise.
def decode_standard_frame(self, can_rx, bitnum):
- # Bit 14: FDF (Flexible Data Format)
- # Has to be sent dominant when FD frame, has to be sent recessive when classic CAN frame.
+ # Bit 14: FDF (Flexible data format)
+ # Has to be sent dominant when FD frame, has to be sent recessive
+ # when classic CAN frame.
if bitnum == 14:
self.fd = True if can_rx else False
+ if self.fd:
+ self.putx([7, ['Flexible data format: %d' % can_rx,
+ 'FDF: %d' % can_rx, 'FDF']])
+ else:
+ self.putx([7, ['Reserved bit 0: %d' % can_rx,
+ 'RB0: %d' % can_rx, 'RB0']])
- self.putx([7, ['Flexible Data Format: %d' % can_rx,
- 'FDF: %d' % can_rx,
- 'FDF']])
-
- # SRR Substitute Remote Request
if self.fd:
- self.put12([8, ['Substitute Remote Request', 'SRR']])
+ # Bit 12: Substitute remote request (SRR) bit
+ self.put12([8, ['Substitute remote request', 'SRR']])
self.dlc_start = 18
else:
# Bit 12: Remote transmission request (RTR) bit
rtr = 'remote' if self.bits[12] == 1 else 'data'
self.put12([8, ['Remote transmission request: %s frame' % rtr,
'RTR: %s frame' % rtr, 'RTR']])
+ self.rtr_type = rtr
self.dlc_start = 15
- # TODO: add Res, BRS and ESI bits when FD format:
- if bitnum == 15:
- if self.fd:
- self.putx([7, ['Reserved: %d' % can_rx, 'R0: %d' % can_rx, 'R0']])
+ if bitnum == 15 and self.fd:
+ self.putx([7, ['Reserved: %d' % can_rx, 'R0: %d' % can_rx, 'R0']])
- if bitnum == 16:
- if self.fd:
- self.putx([7, ['Bit rate switch: %d' % can_rx, 'BRS: %d' % can_rx, 'BRS']])
+ if bitnum == 16 and self.fd:
+ self.putx([7, ['Bit rate switch: %d' % can_rx, 'BRS: %d' % can_rx, 'BRS']])
- if bitnum == 17:
- if self.fd:
- self.putx([7, ['Error state indicator: %d' % can_rx, 'ESI: %d' % can_rx, 'ESI']])
+ if bitnum == 17 and self.fd:
+ self.putx([7, ['Error state indicator: %d' % can_rx, 'ESI: %d' % can_rx, 'ESI']])
# Remember start of DLC (see below).
elif bitnum == self.dlc_start:
# Bits 15-18: Data length code (DLC), in number of bytes (0-8).
elif bitnum == self.dlc_start + 3:
- self.dlc = int(''.join(str(d) for d in self.bits[self.dlc_start:self.dlc_start + 4]), 2)
- self.putb([10, ['Data length code: %d (%d Bytes)' % (self.dlc, self.dlc2len(self.dlc)),
- 'DLC: %d (%d B)' % (self.dlc, self.dlc2len(self.dlc)), 'DLC']])
- self.last_databit = self.dlc_start + 3 + (self.dlc2len(self.dlc) * 8)
+ self.dlc = bitpack_msb(self.bits[self.dlc_start:self.dlc_start + 4])
+ self.putb([10, ['Data length code: %d' % self.dlc,
+ 'DLC: %d' % self.dlc, 'DLC']])
+ self.last_databit = self.dlc_start + 3 + (dlc2len(self.dlc) * 8)
+ if self.dlc > 8 and not self.fd:
+ self.putb([16, ['Data length code (DLC) > 8 is not allowed']])
# Remember all databyte bits, except the very last one.
elif bitnum in range(self.dlc_start + 4, self.last_databit):
# The bits within a data byte are transferred MSB-first.
elif bitnum == self.last_databit:
self.ss_databytebits.append(self.samplenum) # Last databyte bit.
- for i in range(self.dlc2len(self.dlc)):
+ for i in range(dlc2len(self.dlc)):
x = self.dlc_start + 4 + (8 * i)
- b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2)
+ b = bitpack_msb(self.bits[x:x + 8])
+ self.frame_bytes.append(b)
ss = self.ss_databytebits[i * 8]
es = self.ss_databytebits[((i + 1) * 8) - 1]
self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b),
# Remember start of EID (see below).
if bitnum == 14:
self.ss_block = self.samplenum
+ self.fd = False
+ self.dlc_start = 35
# Bits 14-31: Extended identifier (EID[17..0])
elif bitnum == 31:
- self.eid = int(''.join(str(d) for d in self.bits[14:]), 2)
+ self.eid = bitpack_msb(self.bits[14:])
s = '%d (0x%x)' % (self.eid, self.eid)
self.putb([4, ['Extended Identifier: %s' % s,
'Extended ID: %s' % s, 'Extended ID', 'EID']])
- self.fullid = self.id << 18 | self.eid
+ self.fullid = self.ident << 18 | self.eid
s = '%d (0x%x)' % (self.fullid, self.fullid)
self.putb([5, ['Full Identifier: %s' % s, 'Full ID: %s' % s,
'Full ID', 'FID']])
# Bit 32: Remote transmission request (RTR) bit
# Data frame: dominant, remote frame: recessive
# Remote frames do not contain a data field.
+
+ # Remember start of RTR (see below).
if bitnum == 32:
- rtr = 'remote' if can_rx == 1 else 'data'
- self.putx([8, ['Remote transmission request: %s frame' % rtr,
- 'RTR: %s frame' % rtr, 'RTR']])
+ self.ss_bit32 = self.samplenum
+ self.rtr = can_rx
+
+ if not self.fd:
+ rtr = 'remote' if can_rx == 1 else 'data'
+ self.putx([8, ['Remote transmission request: %s frame' % rtr,
+ 'RTR: %s frame' % rtr, 'RTR']])
+ self.rtr_type = rtr
# Bit 33: RB1 (reserved bit)
elif bitnum == 33:
- self.putx([7, ['Reserved bit 1: %d' % can_rx,
- 'RB1: %d' % can_rx, 'RB1']])
+ self.fd = True if can_rx else False
+ if self.fd:
+ self.dlc_start = 37
+ self.putx([7, ['Flexible data format: %d' % can_rx,
+ 'FDF: %d' % can_rx, 'FDF']])
+ self.put32([7, ['Reserved bit 1: %d' % self.rtr,
+ 'RB1: %d' % self.rtr, 'RB1']])
+ else:
+ self.putx([7, ['Reserved bit 1: %d' % can_rx,
+ 'RB1: %d' % can_rx, 'RB1']])
# Bit 34: RB0 (reserved bit)
elif bitnum == 34:
self.putx([7, ['Reserved bit 0: %d' % can_rx,
'RB0: %d' % can_rx, 'RB0']])
+ elif bitnum == 35 and self.fd:
+ self.putx([7, ['Bit rate switch: %d' % can_rx,
+ 'BRS: %d' % can_rx, 'BRS']])
+
+ elif bitnum == 36 and self.fd:
+ self.putx([7, ['Error state indicator: %d' % can_rx,
+ 'ESI: %d' % can_rx, 'ESI']])
+
# Remember start of DLC (see below).
- elif bitnum == 35:
+ elif bitnum == self.dlc_start:
self.ss_block = self.samplenum
# Bits 35-38: Data length code (DLC), in number of bytes (0-8).
- elif bitnum == 38:
- self.dlc = int(''.join(str(d) for d in self.bits[35:38 + 1]), 2)
- self.putb([10, ['Data length code: %d (%d Bytes)' % (self.dlc, self.dlc2len(self.dlc)),
- 'DLC: %d (%d B)' % (self.dlc, self.dlc2len(self.dlc)), 'DLC']])
- self.last_databit = 38 + (self.dlc2len(self.dlc) * 8)
+ elif bitnum == self.dlc_start + 3:
+ self.dlc = bitpack_msb(self.bits[self.dlc_start:self.dlc_start + 4])
+ self.putb([10, ['Data length code: %d' % self.dlc,
+ 'DLC: %d' % self.dlc, 'DLC']])
+ self.last_databit = self.dlc_start + 3 + (dlc2len(self.dlc) * 8)
# Remember all databyte bits, except the very last one.
- elif bitnum in range(39, self.last_databit):
+ elif bitnum in range(self.dlc_start + 4, self.last_databit):
self.ss_databytebits.append(self.samplenum)
# Bits 39-X: Data field (0-8 bytes, depending on DLC)
# The bits within a data byte are transferred MSB-first.
elif bitnum == self.last_databit:
self.ss_databytebits.append(self.samplenum) # Last databyte bit.
- for i in range(self.dlc2len(self.dlc)):
- x = 38 + (8 * i) + 1
- b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2)
+ for i in range(dlc2len(self.dlc)):
+ x = self.dlc_start + 4 + (8 * i)
+ b = bitpack_msb(self.bits[x:x + 8])
+ self.frame_bytes.append(b)
ss = self.ss_databytebits[i * 8]
es = self.ss_databytebits[((i + 1) * 8) - 1]
self.putg(ss, es, [0, ['Data byte %d: 0x%02x' % (i, b),
# Get the index of the current CAN frame bit (without stuff bits).
bitnum = len(self.bits) - 1
+ if self.fd and can_rx:
+ if bitnum == 16 and self.frame_type == 'standard' \
+ or bitnum == 35 and self.frame_type == 'extended':
+ self.dom_edge_seen(force=True)
+ self.set_fast_bitrate()
+
# If this is a stuff bit, remove it from self.bits and ignore it.
if self.is_stuff_bit():
self.putx([15, [str(can_rx)]])
# Bit 0: Start of frame (SOF) bit
if bitnum == 0:
+ self.ss_packet = self.samplenum
self.putx([1, ['Start of frame', 'SOF', 'S']])
if can_rx != 0:
self.putx([16, ['Start of frame (SOF) must be a dominant bit']])
# Bits 1-11: Identifier (ID[10..0])
# The bits ID[10..4] must NOT be all recessive.
elif bitnum == 11:
- self.id = int(''.join(str(d) for d in self.bits[1:]), 2)
- s = '%d (0x%x)' % (self.id, self.id),
+ # BEWARE! Don't clobber the decoder's .id field which is
+ # part of its boiler plate!
+ self.ident = bitpack_msb(self.bits[1:])
+ self.fullid = self.ident
+ s = '%d (0x%x)' % (self.ident, self.ident),
self.putb([3, ['Identifier: %s' % s, 'ID: %s' % s, 'ID']])
- if (self.id & 0x7f0) == 0x7f0:
+ if (self.ident & 0x7f0) == 0x7f0:
self.putb([16, ['Identifier bits 10..4 must not be all recessive']])
# RTR or SRR bit, depending on frame type (gets handled later).
self.dom_edge_seen()
if self.matched[0]:
self.handle_bit(can_rx)
- self.bit_sampled()
projects / libsigrokdecode.git / blobdiff