if bitnum == (self.last_databit + 1):
self.ss_block = self.samplenum
- # CRC sequence (15 bits)
- elif bitnum == (self.last_databit + 15):
+ if self.fd:
+ if self.dlc < 16:
+ self.crc_len = 27 # 17 + SBC + stuff bits
+ else:
+ self.crc_len = 21
+ else:
+ self.crc_len = 15
+
+ # CRC sequence (15 bits, 17 bits or 21 bits)
+ elif bitnum == (self.last_databit + self.crc_len):
+ if self.fd:
+ if self.dlc < 16:
+ crc_type = "CRC-17"
+ else:
+ crc_type = "CRC-21"
+ else:
+ crc_type = "CRC-15"
+
x = self.last_databit + 1
- crc_bits = self.bits[x:x + 15 + 1]
+ crc_bits = self.bits[x:x + self.crc_len + 1]
self.crc = int(''.join(str(d) for d in crc_bits), 2)
- self.putb([11, ['CRC sequence: 0x%04x' % self.crc,
- 'CRC: 0x%04x' % self.crc, 'CRC']])
+ self.putb([11, ['%s sequence: 0x%04x' % (crc_type, self.crc),
+ '%s: 0x%04x' % (crc_type, self.crc), '%s' % crc_type]])
if not self.is_valid_crc(crc_bits):
self.putb([16, ['CRC is invalid']])
# CRC delimiter bit (recessive)
- elif bitnum == (self.last_databit + 16):
+ elif bitnum == (self.last_databit + self.crc_len + 1):
self.putx([12, ['CRC delimiter: %d' % can_rx,
'CRC d: %d' % can_rx, 'CRC d']])
if can_rx != 1:
self.putx([16, ['CRC delimiter must be a recessive bit']])
# ACK slot bit (dominant: ACK, recessive: NACK)
- elif bitnum == (self.last_databit + 17):
+ elif bitnum == (self.last_databit + self.crc_len + 2):
ack = 'ACK' if can_rx == 0 else 'NACK'
self.putx([13, ['ACK slot: %s' % ack, 'ACK s: %s' % ack, 'ACK s']])
# ACK delimiter bit (recessive)
- elif bitnum == (self.last_databit + 18):
+ elif bitnum == (self.last_databit + self.crc_len + 3):
self.putx([14, ['ACK delimiter: %d' % can_rx,
'ACK d: %d' % can_rx, 'ACK d']])
if can_rx != 1:
self.putx([16, ['ACK delimiter must be a recessive bit']])
# Remember start of EOF (see below).
- elif bitnum == (self.last_databit + 19):
+ elif bitnum == (self.last_databit + self.crc_len + 4):
self.ss_block = self.samplenum
# End of frame (EOF), 7 recessive bits
- elif bitnum == (self.last_databit + 25):
+ elif bitnum == (self.last_databit + self.crc_len + 11):
self.putb([2, ['End of frame', 'EOF', 'E']])
if self.rawbits[-7:] != [1, 1, 1, 1, 1, 1, 1]:
self.putb([16, ['End of frame (EOF) must be 7 recessive bits']])
self.fd = True if can_rx else False
self.putx([7, ['Flexible Data Format: %d' % can_rx,
- 'FDF: %d' % can_rx, 'FDF']])
+ 'FDF: %d' % can_rx,
+ 'FDF']])
# SRR Substitute Remote Request
if self.fd:
self.put12([8, ['Substitute Remote Request', 'SRR']])
+ self.dlc_start = 18
else:
# Bit 12: Remote transmission request (RTR) bit
# Data frame: dominant, remote frame: recessive
rtr = 'remote' if self.bits[12] == 1 else 'data'
self.put12([8, ['Remote transmission request: %s frame' % rtr,
'RTR: %s frame' % rtr, 'RTR']])
+ self.dlc_start = 15
# TODO: add Res, BRS and ESI bits when FD format:
+ if bitnum == 15:
+ if self.fd:
+ self.putx([7, ['Reserved: %d' % can_rx, 'R0: %d' % can_rx, 'R0']])
+
+ if bitnum == 16:
+ if self.fd:
+ self.putx([7, ['Bit rate switch: %d' % can_rx, 'BRS: %d' % can_rx, 'BRS']])
+ if bitnum == 17:
+ if self.fd:
+ self.putx([7, ['Error state indicator: %d' % can_rx, 'ESI: %d' % can_rx, 'ESI']])
# Remember start of DLC (see below).
- elif bitnum == 15:
+ elif bitnum == self.dlc_start:
self.ss_block = self.samplenum
# Bits 15-18: Data length code (DLC), in number of bytes (0-8).
- elif bitnum == 18:
- self.dlc = int(''.join(str(d) for d in self.bits[15:18 + 1]), 2)
+ elif bitnum == self.dlc_start + 3:
+ self.dlc = int(''.join(str(d) for d in self.bits[self.dlc_start:self.dlc_start + 4]), 2)
self.putb([10, ['Data length code: %d' % self.dlc,
'DLC: %d' % self.dlc, 'DLC']])
- self.last_databit = 18 + (self.dlc * 8)
+ self.last_databit = self.dlc_start + 3 + (self.dlc * 8)
if self.dlc > 8:
self.putb([16, ['Data length code (DLC) > 8 is not allowed']])
# Remember all databyte bits, except the very last one.
- elif bitnum in range(19, self.last_databit):
+ elif bitnum in range(self.dlc_start + 4, self.last_databit):
self.ss_databytebits.append(self.samplenum)
# Bits 19-X: Data field (0-8 bytes, depending on DLC)
elif bitnum == self.last_databit:
self.ss_databytebits.append(self.samplenum) # Last databyte bit.
for i in range(self.dlc):
- x = 18 + (8 * i) + 1
+ x = self.dlc_start + 4 + (8 * i)
b = int(''.join(str(d) for d in self.bits[x:x + 8]), 2)
ss = self.ss_databytebits[i * 8]
es = self.ss_databytebits[((i + 1) * 8) - 1]
# Bits 14-X: Frame-type dependent, passed to the resp. handlers.
elif bitnum >= 14:
- self.fd = True if can_rx else False
-
if self.frame_type == 'standard':
done = self.decode_standard_frame(can_rx, bitnum)
else:
projects / libsigrokdecode.git / blobdiff