Add PD tags handling and some tags

[libsigrokdecode.git] / decoders / can / pd.py

diff --git a/decoders/can/pd.py b/decoders/can/pd.py
index f1adef1ada54560bda815689ec5f0301051e095c..1084fe896fbe4c1f12d32e896c2a2f58caf61aef 100644 (file)
--- a/decoders/can/pd.py
+++ b/decoders/can/pd.py
@@ -23,7 +23,7 @@ class SamplerateError(Exception):
     pass
 
 class Decoder(srd.Decoder):
-    api_version = 2
+    api_version = 3
     id = 'can'
     name = 'CAN'
     longname = 'Controller Area Network'
@@ -31,6 +31,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['can']
+    tags = ['Logic', 'Bus']
     channels = (
         {'id': 'can_rx', 'name': 'CAN RX', 'desc': 'CAN bus line'},
     )
@@ -65,6 +66,9 @@ class Decoder(srd.Decoder):
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.samplerate = None
         self.reset_variables()
 
@@ -75,11 +79,11 @@ class Decoder(srd.Decoder):
         if key == srd.SRD_CONF_SAMPLERATE:
             self.samplerate = value
             self.bit_width = float(self.samplerate) / float(self.options['bitrate'])
-            self.bitpos = (self.bit_width / 100.0) * self.options['sample_point']
+            self.sample_point = (self.bit_width / 100.0) * self.options['sample_point']
 
     # Generic helper for CAN bit annotations.
     def putg(self, ss, es, data):
-        left, right = int(self.bitpos), int(self.bit_width - self.bitpos)
+        left, right = int(self.sample_point), int(self.bit_width - self.sample_point)
         self.put(ss - left, es + right, self.out_ann, data)
 
     # Single-CAN-bit annotation using the current samplenum.
@@ -105,16 +109,32 @@ class Decoder(srd.Decoder):
         self.ss_bit12 = None
         self.ss_databytebits = []
 
-    # Return True if we reached the desired bit position, False otherwise.
-    def reached_bit(self, bitnum):
-        bitpos = int(self.sof + (self.bit_width * bitnum) + self.bitpos)
-        if self.samplenum >= bitpos:
-            return True
-        return False
+    # Poor man's clock synchronization. Use signal edges which change to
+    # dominant state in rather simple ways. This naive approach is neither
+    # aware of the SYNC phase's width nor the specific location of the edge,
+    # but improves the decoder's reliability when the input signal's bitrate
+    # does not exactly match the nominal rate.
+    def dom_edge_seen(self, force = False):
+        self.dom_edge_snum = self.samplenum
+        self.dom_edge_bcount = self.curbit
+
+    def bit_sampled(self):
+        # EMPTY
+        pass
+
+    # Determine the position of the next desired bit's sample point.
+    def get_sample_point(self, bitnum):
+        samplenum = self.dom_edge_snum
+        samplenum += int(self.bit_width * (bitnum - self.dom_edge_bcount))
+        samplenum += int(self.sample_point)
+        return samplenum
 
     def is_stuff_bit(self):
         # CAN uses NRZ encoding and bit stuffing.
         # After 5 identical bits, a stuff bit of opposite value is added.
+        # But not in the CRC delimiter, ACK, and end of frame fields.
+        if len(self.bits) > self.last_databit + 17:
+            return False
         last_6_bits = self.rawbits[-6:]
         if last_6_bits not in ([0, 0, 0, 0, 0, 1], [1, 1, 1, 1, 1, 0]):
             return False
@@ -371,22 +391,24 @@ class Decoder(srd.Decoder):
 
         self.curbit += 1
 
-    def decode(self, ss, es, data):
+    def decode(self):
         if not self.samplerate:
             raise SamplerateError('Cannot decode without samplerate.')
-        for (self.samplenum, pins) in data:
-
-            (can_rx,) = pins
 
+        while True:
             # State machine.
             if self.state == 'IDLE':
                 # Wait for a dominant state (logic 0) on the bus.
-                if can_rx == 1:
-                    continue
+                (can_rx,) = self.wait({0: 'l'})
                 self.sof = self.samplenum
+                self.dom_edge_seen(force = True)
                 self.state = 'GET BITS'
             elif self.state == 'GET BITS':
                 # Wait until we're in the correct bit/sampling position.
-                if not self.reached_bit(self.curbit):
-                    continue
-                self.handle_bit(can_rx)
+                pos = self.get_sample_point(self.curbit)
+                (can_rx,) = self.wait([{'skip': pos - self.samplenum}, {0: 'f'}])
+                if self.matched[1]:
+                    self.dom_edge_seen()
+                if self.matched[0]:
+                    self.handle_bit(can_rx)
+                    self.bit_sampled()