- self.putx([7, ['Reserved bit 1: %d' % can_rx,
- 'RB1: %d' % can_rx, 'RB1']])
+ self.fd = True if can_rx else False
+ if self.fd:
+ self.dlc_start = 37
+ self.putx([7, ['Flexible data format: %d' % can_rx,
+ 'FDF: %d' % can_rx, 'FDF']])
+ self.put32([7, ['Reserved bit 1: %d' % self.rtr,
+ 'RB1: %d' % self.rtr, 'RB1']])
+ else:
+ self.putx([7, ['Reserved bit 1: %d' % can_rx,
+ 'RB1: %d' % can_rx, 'RB1']])