cfp: Drop unused self.out_python.

[libsigrokdecode.git] / decoders / avr_pdi / pd.py

diff --git a/decoders/avr_pdi/pd.py b/decoders/avr_pdi/pd.py
index 179350da1fda7fd4fc4e8208f9db1cb77fb66f4f..7fedbbdfe18e4e18b8447134adc271591c143d21 100644 (file)
--- a/decoders/avr_pdi/pd.py
+++ b/decoders/avr_pdi/pd.py
@@ -154,6 +154,9 @@ class Decoder(srd.Decoder):
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.samplerate = None
         self.clear_state()
 
@@ -543,7 +546,7 @@ class Decoder(srd.Decoder):
         # Reset internal state for the next frame.
         self.bits = []
 
-    def handle_clk_edge(self, samplenum, clock_pin, data_pin):
+    def handle_clk_edge(self, clock_pin, data_pin):
         # Sample the data line on rising clock edges. Always, for TX and for
         # RX bytes alike.
         if clock_pin == 1:
@@ -556,7 +559,7 @@ class Decoder(srd.Decoder):
         # periods (avoid interpreting the DATA line when the "enabled" state
         # has not yet been determined).
         self.ss_last_fall = self.ss_curr_fall
-        self.ss_curr_fall = samplenum
+        self.ss_curr_fall = self.samplenum
         if self.ss_last_fall is None:
             return
 
@@ -567,5 +570,4 @@ class Decoder(srd.Decoder):
 
     def decode(self):
         while True:
-            clock_pin, data_pin = self.wait({0: 'e'})
-            self.handle_clk_edge(self.samplenum, clock_pin, data_pin)
+            self.handle_clk_edge(*self.wait({0: 'e'}))