Add PD tags handling and some tags

[libsigrokdecode.git] / decoders / avr_pdi / pd.py

diff --git a/decoders/avr_pdi/pd.py b/decoders/avr_pdi/pd.py
index 179350da1fda7fd4fc4e8208f9db1cb77fb66f4f..184e632af850832b8e9490b9247553f0356bf439 100644 (file)
--- a/decoders/avr_pdi/pd.py
+++ b/decoders/avr_pdi/pd.py
@@ -120,6 +120,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['pdi']
+    tags = ['Logic', 'MCU Debugging']
     channels = (
         {'id': 'reset', 'name': 'RESET', 'desc': 'RESET / PDI_CLK'},
         {'id': 'data', 'name': 'DATA', 'desc': 'PDI_DATA'},
@@ -154,6 +155,9 @@ class Decoder(srd.Decoder):
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.samplerate = None
         self.clear_state()
 
@@ -543,7 +547,7 @@ class Decoder(srd.Decoder):
         # Reset internal state for the next frame.
         self.bits = []
 
-    def handle_clk_edge(self, samplenum, clock_pin, data_pin):
+    def handle_clk_edge(self, clock_pin, data_pin):
         # Sample the data line on rising clock edges. Always, for TX and for
         # RX bytes alike.
         if clock_pin == 1:
@@ -556,7 +560,7 @@ class Decoder(srd.Decoder):
         # periods (avoid interpreting the DATA line when the "enabled" state
         # has not yet been determined).
         self.ss_last_fall = self.ss_curr_fall
-        self.ss_curr_fall = samplenum
+        self.ss_curr_fall = self.samplenum
         if self.ss_last_fall is None:
             return
 
@@ -567,5 +571,4 @@ class Decoder(srd.Decoder):
 
     def decode(self):
         while True:
-            clock_pin, data_pin = self.wait({0: 'e'})
-            self.handle_clk_edge(self.samplenum, clock_pin, data_pin)
+            self.handle_clk_edge(*self.wait({0: 'e'}))