license: remove FSF postal address from boiler plate license text

[libsigrokdecode.git] / decoders / am230x / pd.py

diff --git a/decoders/am230x/pd.py b/decoders/am230x/pd.py
index fd1e825e19f7ff4bd489b638eaa85757391ef7e1..f76cab20b9f7329556280e0b9fe46e9dbc50afaf 100644 (file)
--- a/decoders/am230x/pd.py
+++ b/decoders/am230x/pd.py
@@ -14,8 +14,7 @@
 ## GNU General Public License for more details.
 ##
 ## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## along with this program; if not, see <http://www.gnu.org/licenses/>.
 ##
 
 import sigrokdecode as srd
@@ -35,11 +34,11 @@ class SamplerateError(Exception):
     pass
 
 class Decoder(srd.Decoder):
-    api_version = 2
+    api_version = 3
     id = 'am230x'
-    name = 'AM230x/DHTxx'
-    longname = 'Aosong AM230x/DHTxx'
-    desc = 'Aosong AM230x/DHTxx humidity/temperature sensor protocol.'
+    name = 'AM230x/DHTxx/RHTxx'
+    longname = 'Aosong AM230x/DHTxx/RHTxx'
+    desc = 'Aosong AM230x/DHTxx/RHTxx humidity/temperature sensor protocol.'
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['am230x']
@@ -48,7 +47,7 @@ class Decoder(srd.Decoder):
     )
     options = (
         {'id': 'device', 'desc': 'Device type',
-            'default': 'am230x', 'values': ('am230x', 'dht11')},
+            'default': 'am230x', 'values': ('am230x/rht', 'dht11')},
     )
     annotations = (
         ('start', 'Start'),
@@ -77,7 +76,6 @@ class Decoder(srd.Decoder):
 
     def reset(self):
         self.state = 'WAIT FOR START LOW'
-        self.samplenum = 0
         self.fall = 0
         self.rise = 0
         self.bits = []
@@ -123,13 +121,16 @@ class Decoder(srd.Decoder):
             checksum += self.bits2num(bitlist[i-8:i])
         return checksum % 256
 
-    def __init__(self, **kwargs):
+    def __init__(self):
         self.samplerate = None
         self.reset()
 
     def start(self):
         self.out_ann = self.register(srd.OUTPUT_ANN)
 
+        # Assume that the initial pin state is high (logic 1).
+        self.initial_pins = [1]
+
     def metadata(self, key, value):
         if key != srd.SRD_CONF_SAMPLERATE:
             return
@@ -164,27 +165,24 @@ class Decoder(srd.Decoder):
                 self.state = 'WAIT FOR END'
             self.bytepos.append(self.samplenum)
 
-    def decode(self, ss, es, data):
+    def decode(self):
         if not self.samplerate:
             raise SamplerateError('Cannot decode without samplerate.')
-        for (self.samplenum, (sda,)) in data:
+        while True:
             # State machine.
             if self.state == 'WAIT FOR START LOW':
-                if sda != 0:
-                    continue
+                self.wait({0: 'f'})
                 self.fall = self.samplenum
                 self.state = 'WAIT FOR START HIGH'
             elif self.state == 'WAIT FOR START HIGH':
-                if sda != 1:
-                    continue
+                self.wait({0: 'r'})
                 if self.is_valid('START LOW'):
                     self.rise = self.samplenum
                     self.state = 'WAIT FOR RESPONSE LOW'
                 else:
                     self.reset()
             elif self.state == 'WAIT FOR RESPONSE LOW':
-                if sda != 0:
-                    continue
+                self.wait({0: 'f'})
                 if self.is_valid('START HIGH'):
                     self.putfs([0, ['Start', 'S']])
                     self.fall = self.samplenum
@@ -192,16 +190,14 @@ class Decoder(srd.Decoder):
                 else:
                     self.reset()
             elif self.state == 'WAIT FOR RESPONSE HIGH':
-                if sda != 1:
-                    continue
+                self.wait({0: 'r'})
                 if self.is_valid('RESPONSE LOW'):
                     self.rise = self.samplenum
                     self.state = 'WAIT FOR FIRST BIT'
                 else:
                     self.reset()
             elif self.state == 'WAIT FOR FIRST BIT':
-                if sda != 0:
-                    continue
+                self.wait({0: 'f'})
                 if self.is_valid('RESPONSE HIGH'):
                     self.putfs([1, ['Response', 'R']])
                     self.fall = self.samplenum
@@ -210,16 +206,14 @@ class Decoder(srd.Decoder):
                 else:
                     self.reset()
             elif self.state == 'WAIT FOR BIT HIGH':
-                if sda != 1:
-                    continue
+                self.wait({0: 'r'})
                 if self.is_valid('BIT LOW'):
                     self.rise = self.samplenum
                     self.state = 'WAIT FOR BIT LOW'
                 else:
                     self.reset()
             elif self.state == 'WAIT FOR BIT LOW':
-                if sda != 0:
-                    continue
+                self.wait({0: 'f'})
                 if self.is_valid('BIT 0 HIGH'):
                     bit = 0
                 elif self.is_valid('BIT 1 HIGH'):
@@ -229,7 +223,6 @@ class Decoder(srd.Decoder):
                     continue
                 self.handle_byte(bit)
             elif self.state == 'WAIT FOR END':
-                if sda != 1:
-                    continue
+                self.wait({0: 'r'})
                 self.putfs([3, ['End', 'E']])
                 self.reset()