ad79x0: Reduce unnecessarily many voltage formats.

[libsigrokdecode.git] / decoders / ad79x0 / pd.py

diff --git a/decoders/ad79x0/pd.py b/decoders/ad79x0/pd.py
index 9f3a1677aaa015d1642bfe8b42dc7de0ea611ddb..d966ed947e9aa12e10531a84a95ddc265ae298f2 100644 (file)
--- a/decoders/ad79x0/pd.py
+++ b/decoders/ad79x0/pd.py
@@ -25,7 +25,7 @@ modes = {
     2: ['Power Up Mode', 'Power Up', 'PU'],
 }
 
-input_voltage_format = ['%fV', '%fV', '%.6fV', '%.2fV']
+input_voltage_format = ['%.6fV', '%.2fV']
 
 validation = {
     'invalid': ['Invalid data', 'Invalid', 'N/A'],
@@ -42,15 +42,15 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['spi']
     outputs = []
-    tags = ['Display']
+    tags = ['IC', 'Analog/digital']
     annotations = (
         ('mode', 'Mode'),
-        ('data', 'Data'),
+        ('voltage', 'Voltage'),
         ('validation', 'Validation'),
     )
     annotation_rows = (
-        ('mode', 'Mode', (0,)),
-        ('data', 'Converted data', (1,)),
+        ('modes', 'Modes', (0,)),
+        ('voltages', 'Voltages', (1,)),
         ('data_validation', 'Data validation', (2,)),
     )
     options = (