# decoded register access).
import sigrokdecode as srd
+from common.srdhelper import SrdIntEnum
class ChannelError(Exception):
pass
-class Pins:
- (SYNC, BIT_CLK, SDATA_OUT, SDATA_IN, RESET) = range(5)
-
-class Ann:
- (
- BITS_OUT, BITS_IN,
- SLOT_OUT_RAW, SLOT_OUT_TAG, SLOT_OUT_ADDR, SLOT_OUT_DATA,
- SLOT_OUT_03, SLOT_OUT_04, SLOT_OUT_05, SLOT_OUT_06,
- SLOT_OUT_07, SLOT_OUT_08, SLOT_OUT_09, SLOT_OUT_10,
- SLOT_OUT_11, SLOT_OUT_IO,
- SLOT_IN_RAW, SLOT_IN_TAG, SLOT_IN_ADDR, SLOT_IN_DATA,
- SLOT_IN_03, SLOT_IN_04, SLOT_IN_05, SLOT_IN_06,
- SLOT_IN_07, SLOT_IN_08, SLOT_IN_09, SLOT_IN_10,
- SLOT_IN_11, SLOT_IN_IO,
- WARN, ERROR,
- ) = range(32)
- (
- BIN_FRAME_OUT,
- BIN_FRAME_IN,
- BIN_SLOT_RAW_OUT,
- BIN_SLOT_RAW_IN,
- ) = range(4)
+Pin = SrdIntEnum.from_str('Pin', 'SYNC BIT_CLK SDATA_OUT SDATA_IN RESET')
+
+slots = 'TAG ADDR DATA 03 04 05 06 07 08 09 10 11 IO'.split()
+a = 'BITS_OUT BITS_IN SLOT_RAW_OUT SLOT_RAW_IN WARN ERROR'.split() + \
+ ['SLOT_OUT_' + s for s in slots] + ['SLOT_IN_' + s for s in slots]
+Ann = SrdIntEnum.from_list('Ann', a)
+
+Bin = SrdIntEnum.from_str('Bin', 'FRAME_OUT FRAME_IN SLOT_RAW_OUT SLOT_RAW_IN')
class Decoder(srd.Decoder):
api_version = 3
('bit-out', 'Output bit'),
('bit-in', 'Input bit'),
('slot-out-raw', 'Output raw value'),
+ ('slot-in-raw', 'Input raw value'),
+ ('warning', 'Warning'),
+ ('error', 'Error'),
('slot-out-tag', 'Output TAG'),
('slot-out-cmd-addr', 'Output command address'),
('slot-out-cmd-data', 'Output command data'),
('slot-out-10', 'Output slot 10'),
('slot-out-11', 'Output slot 11'),
('slot-out-io-ctrl', 'Output I/O control'),
- ('slot-in-raw', 'Input raw value'),
('slot-in-tag', 'Input TAG'),
('slot-in-sts-addr', 'Input status address'),
('slot-in-sts-data', 'Input status data'),
# CMD ADDR: 'r/w', 'addr', 'unused'
# CMD DATA: 'data', 'unused'
# 3-11: 'data', 'unused', 'double data'
- ('warning', 'Warning'),
- ('error', 'Error'),
)
annotation_rows = (
('bits-out', 'Output bits', (Ann.BITS_OUT,)),
- ('slots-out-raw', 'Output numbers', (Ann.SLOT_OUT_RAW,)),
- ('slots-out', 'Output slots', (
- Ann.SLOT_OUT_TAG, Ann.SLOT_OUT_ADDR, Ann.SLOT_OUT_DATA,
- Ann.SLOT_OUT_03, Ann.SLOT_OUT_04, Ann.SLOT_OUT_05, Ann.SLOT_OUT_06,
- Ann.SLOT_OUT_07, Ann.SLOT_OUT_08, Ann.SLOT_OUT_09, Ann.SLOT_OUT_10,
- Ann.SLOT_OUT_11, Ann.SLOT_OUT_IO,)),
+ ('slots-out-raw', 'Output numbers', (Ann.SLOT_RAW_OUT,)),
+ ('slots-out', 'Output slots', Ann.prefixes('SLOT_OUT_')),
('bits-in', 'Input bits', (Ann.BITS_IN,)),
- ('slots-in-raw', 'Input numbers', (Ann.SLOT_IN_RAW,)),
- ('slots-in', 'Input slots', (
- Ann.SLOT_IN_TAG, Ann.SLOT_IN_ADDR, Ann.SLOT_IN_DATA,
- Ann.SLOT_IN_03, Ann.SLOT_IN_04, Ann.SLOT_IN_05, Ann.SLOT_IN_06,
- Ann.SLOT_IN_07, Ann.SLOT_IN_08, Ann.SLOT_IN_09, Ann.SLOT_IN_10,
- Ann.SLOT_IN_11, Ann.SLOT_IN_IO,)),
+ ('slots-in-raw', 'Input numbers', (Ann.SLOT_RAW_IN,)),
+ ('slots-in', 'Input slots', Ann.prefixes('SLOT_IN_')),
('warnings', 'Warnings', (Ann.WARN,)),
('errors', 'Errors', (Ann.ERROR,)),
)
def flush_frame_bits(self):
# Flush raw frame bits to binary annotation.
- anncls = Ann.BIN_FRAME_OUT
data = self.frame_bits_out[:]
count = len(data)
data = self.bits_to_bin_ann(data)
- self.putb(0, count, anncls, data)
+ self.putb(0, count, Bin.FRAME_OUT, data)
- anncls = Ann.BIN_FRAME_IN
data = self.frame_bits_in[:]
count = len(data)
data = self.bits_to_bin_ann(data)
- self.putb(0, count, anncls, data)
+ self.putb(0, count, Bin.FRAME_IN, data)
def start_frame(self, ss):
# Mark the start of a frame.
# that happens to be valid. For an improved implementation, it
# either takes user provided specs or more smarts like observing
# register access (if the capture includes it).
- anncls = Ann.BIN_SLOT_RAW_OUT if is_out else Ann.BIN_SLOT_RAW_IN
+ anncls = Bin.SLOT_RAW_OUT if is_out else Bin.SLOT_RAW_IN
data_bin = data >> 4
data_bin &= 0xffff
data_bin = data_bin.to_bytes(2, byteorder = 'big')
slot_es = self.frame_ss_list[have_len]
if slot_data_out is not None:
slot_text = self.int_to_nibble_text(slot_data_out, slot_len)
- self.putx(slot_ss, slot_es, Ann.SLOT_OUT_RAW, [slot_text])
+ self.putx(slot_ss, slot_es, Ann.SLOT_RAW_OUT, [slot_text])
if slot_data_in is not None:
slot_text = self.int_to_nibble_text(slot_data_in, slot_len)
- self.putx(slot_ss, slot_es, Ann.SLOT_IN_RAW, [slot_text])
+ self.putx(slot_ss, slot_es, Ann.SLOT_RAW_IN, [slot_text])
self.handle_slot(slot_idx, slot_data_out, slot_data_in)
def decode(self):
- have_sdo = self.has_channel(Pins.SDATA_OUT)
- have_sdi = self.has_channel(Pins.SDATA_IN)
+ have_sdo = self.has_channel(Pin.SDATA_OUT)
+ have_sdi = self.has_channel(Pin.SDATA_IN)
if not have_sdo and not have_sdi:
raise ChannelError('Either SDATA_OUT or SDATA_IN (or both) are required.')
- have_reset = self.has_channel(Pins.RESET)
+ have_reset = self.has_channel(Pin.RESET)
# Data is sampled at falling CLK edges. Annotations need to span
# the period between rising edges. SYNC rises one cycle _before_
# and advance to the start of a bit time. Then keep getting the
# samples and the end of all subsequent bit times.
prev_sync = [None, None, None]
- pins = self.wait({Pins.BIT_CLK: 'e'})
- if pins[Pins.BIT_CLK] == 0:
- prev_sync[-1] = pins[Pins.SYNC]
- pins = self.wait({Pins.BIT_CLK: 'r'})
+ pins = self.wait({Pin.BIT_CLK: 'e'})
+ if pins[Pin.BIT_CLK] == 0:
+ prev_sync[-1] = pins[Pin.SYNC]
+ pins = self.wait({Pin.BIT_CLK: 'r'})
bit_ss = self.samplenum
while True:
- pins = self.wait({Pins.BIT_CLK: 'f'})
+ pins = self.wait({Pin.BIT_CLK: 'f'})
prev_sync.pop(0)
- prev_sync.append(pins[Pins.SYNC])
- self.wait({Pins.BIT_CLK: 'r'})
+ prev_sync.append(pins[Pin.SYNC])
+ self.wait({Pin.BIT_CLK: 'r'})
if prev_sync[0] == 0 and prev_sync[1] == 1:
self.start_frame(bit_ss)
self.handle_bits(bit_ss, self.samplenum,
- pins[Pins.SDATA_OUT] if have_sdo else None,
- pins[Pins.SDATA_IN] if have_sdi else None)
+ pins[Pin.SDATA_OUT] if have_sdo else None,
+ pins[Pin.SDATA_IN] if have_sdi else None)
bit_ss = self.samplenum
projects / libsigrokdecode.git / blobdiff