[libsigrokdecode.git] / decoders / usb_signalling / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

import sigrokdecode as srd

'''
OUTPUT_PYTHON format:

Packet:
[<ptype>, <pdata>]

<ptype>, <pdata>:
 - 'SOP', None
 - 'SYM', <sym>
 - 'BIT', <bit>
 - 'STUFF BIT', None
 - 'EOP', None

<sym>:
 - 'J', 'K', 'SE0', or 'SE1'

<bit>:
 - 0 or 1
 - Note: Symbols like SE0, SE1, and the J that's part of EOP don't yield 'BIT'.
'''

# Low-/full-speed symbols.
# Note: Low-speed J and K are inverted compared to the full-speed J and K!
symbols = {
    'low-speed': {
        # (<dp>, <dm>): <symbol/state>
        (0, 0): 'SE0',
        (1, 0): 'K',
        (0, 1): 'J',
        (1, 1): 'SE1',
    },
    'full-speed': {
        # (<dp>, <dm>): <symbol/state>
        (0, 0): 'SE0',
        (1, 0): 'J',
        (0, 1): 'K',
        (1, 1): 'SE1',
    },
}

bitrates = {
    'low-speed': 1500000,   # 1.5Mb/s (+/- 1.5%)
    'full-speed': 12000000, # 12Mb/s (+/- 0.25%)
}

sym_idx = {
    'J': 0,
    'K': 1,
    'SE0': 2,
    'SE1': 3,
}

class SamplerateError(Exception):
    pass

class Decoder(srd.Decoder):
    api_version = 2
    id = 'usb_signalling'
    name = 'USB signalling'
    longname = 'Universal Serial Bus (LS/FS) signalling'
    desc = 'USB (low-speed and full-speed) signalling protocol.'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['usb_signalling']
    channels = (
        {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
        {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
    )
    options = (
        {'id': 'signalling', 'desc': 'Signalling',
            'default': 'full-speed', 'values': ('full-speed', 'low-speed')},
    )
    annotations = (
        ('sym-j', 'J symbol'),
        ('sym-k', 'K symbol'),
        ('sym-se0', 'SE0 symbol'),
        ('sym-se1', 'SE1 symbol'),
        ('sop', 'Start of packet (SOP)'),
        ('eop', 'End of packet (EOP)'),
        ('bit', 'Bit'),
        ('stuffbit', 'Stuff bit'),
    )
    annotation_rows = (
        ('bits', 'Bits', (4, 5, 6, 7)),
        ('symbols', 'Symbols', (0, 1, 2, 3)),
    )

    def __init__(self):
        self.samplerate = None
        self.oldsym = 'J' # The "idle" state is J.
        self.ss_sop = None
        self.ss_block = None
        self.samplenum = 0
        self.syms = []
        self.bitrate = None
        self.bitwidth = None
        self.samplepos = None
        self.samplenum_target = None
        self.samplenum_edge = None
        self.oldpins = None
        self.edgepins = None
        self.consecutive_ones = 0
        self.state = 'IDLE'

    def start(self):
        self.out_python = self.register(srd.OUTPUT_PYTHON)
        self.out_ann = self.register(srd.OUTPUT_ANN)

    def metadata(self, key, value):
        if key == srd.SRD_CONF_SAMPLERATE:
            self.samplerate = value
            self.bitrate = bitrates[self.options['signalling']]
            self.bitwidth = float(self.samplerate) / float(self.bitrate)
            self.halfbit = int(self.bitwidth / 2)

    def putpx(self, data):
        self.put(self.samplenum, self.samplenum, self.out_python, data)

    def putx(self, data):
        self.put(self.samplenum, self.samplenum, self.out_ann, data)

    def putpm(self, data):
        s, h = self.samplenum, self.halfbit
        self.put(self.ss_block - h, s + h, self.out_python, data)

    def putm(self, data):
        s, h = self.samplenum, self.halfbit
        self.put(self.ss_block - h, s + h, self.out_ann, data)

    def putpb(self, data):
        s, h = self.samplenum, self.halfbit
        self.put(self.samplenum_edge, s + h, self.out_python, data)

    def putb(self, data):
        s, h = self.samplenum, self.halfbit
        self.put(self.samplenum_edge, s + h, self.out_ann, data)

    def set_new_target_samplenum(self):
        self.samplepos += self.bitwidth;
        self.samplenum_target = int(self.samplepos)
        self.samplenum_edge = int(self.samplepos - (self.bitwidth / 2))

    def wait_for_sop(self, sym):
        # Wait for a Start of Packet (SOP), i.e. a J->K symbol change.
        if sym != 'K':
            self.oldsym = sym
            return
        self.ss_sop = self.samplenum
        self.samplepos = self.ss_sop - (self.bitwidth / 2) + 0.5
        self.set_new_target_samplenum()
        self.putpx(['SOP', None])
        self.putx([4, ['SOP', 'S']])
        self.state = 'GET BIT'

    def handle_bit(self, sym, b):
        if self.consecutive_ones == 6 and b == '0':
            # Stuff bit.
            self.putpb(['STUFF BIT', None])
            self.putb([7, ['Stuff bit: %s' % b, 'SB: %s' % b, '%s' % b]])
            self.putb([sym_idx[sym], ['%s' % sym]])
            self.consecutive_ones = 0
        else:
            # Normal bit (not a stuff bit).
            self.putpb(['BIT', b])
            self.putb([6, ['%s' % b]])
            self.putb([sym_idx[sym], ['%s' % sym]])
            if b == '1':
                self.consecutive_ones += 1
            else:
                self.consecutive_ones = 0

    def get_eop(self, sym):
        # EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J.
        self.syms.append(sym)
        self.putpb(['SYM', sym])
        self.putb([sym_idx[sym], ['%s' % sym, '%s' % sym[0]]])
        self.set_new_target_samplenum()
        self.oldsym = sym
        if self.syms[-2:] == ['SE0', 'J']:
            # Got an EOP.
            self.putpm(['EOP', None])
            self.putm([5, ['EOP', 'E']])
            self.syms, self.state = [], 'IDLE'
            self.consecutive_ones = 0
            self.bitwidth = float(self.samplerate) / float(self.bitrate)

    def get_bit(self, sym):
        if sym == 'SE0':
            # Start of an EOP. Change state, run get_eop() for this bit.
            self.state = 'GET EOP'
            self.ss_block = self.samplenum
            self.get_eop(sym)
            return
        self.syms.append(sym)
        self.putpb(['SYM', sym])
        b = '0' if self.oldsym != sym else '1'
        if (self.oldsym != sym):
            # edge
            edgesym = symbols[self.options['signalling']][tuple(self.edgepins)]
            if (edgesym not in ('SE0', 'SE1')):
                if (edgesym == sym):
                    self.bitwidth = self.bitwidth - (0.001 * self.bitwidth)
                    self.samplepos = self.samplepos - (0.01 * self.bitwidth)
                else:
                    self.bitwidth = self.bitwidth + (0.001 * self.bitwidth)
                    self.samplepos = self.samplepos + (0.01 * self.bitwidth)
        self.handle_bit(sym, b)
        self.set_new_target_samplenum()
        self.oldsym = sym

    def decode(self, ss, es, data):
        if not self.samplerate:
            raise SamplerateError('Cannot decode without samplerate.')
        for (self.samplenum, pins) in data:
            # State machine.
            if self.state == 'IDLE':
                # Ignore identical samples early on (for performance reasons).
                if self.oldpins == pins:
                    continue
                self.oldpins = pins
                sym = symbols[self.options['signalling']][tuple(pins)]
                self.wait_for_sop(sym)
                self.edgepins = pins
            elif self.state in ('GET BIT', 'GET EOP'):
                # Wait until we're in the middle of the desired bit.
                if self.samplenum == self.samplenum_edge:
                    self.edgepins = pins
                if self.samplenum < self.samplenum_target:
                    continue
                sym = symbols[self.options['signalling']][tuple(pins)]
                if self.state == 'GET BIT':
                    self.get_bit(sym)
                elif self.state == 'GET EOP':
                    self.get_eop(sym)
Commit	Line	Data
	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
	5	## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
	6	##
	7	## This program is free software; you can redistribute it and/or modify
	8	## it under the terms of the GNU General Public License as published by
	9	## the Free Software Foundation; either version 2 of the License, or
	10	## (at your option) any later version.
	11	##
	12	## This program is distributed in the hope that it will be useful,
	13	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	## GNU General Public License for more details.
	16	##
	17	## You should have received a copy of the GNU General Public License
	18	## along with this program; if not, write to the Free Software
	19	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	20	##
	21
	22	import sigrokdecode as srd
	23
	24	'''
	25	OUTPUT_PYTHON format:
	26
	27	Packet:
	28	[<ptype>, <pdata>]
	29
	30	<ptype>, <pdata>:
	31	- 'SOP', None
	32	- 'SYM', <sym>
	33	- 'BIT', <bit>
	34	- 'STUFF BIT', None
	35	- 'EOP', None
	36
	37	<sym>:
	38	- 'J', 'K', 'SE0', or 'SE1'
	39
	40	<bit>:
	41	- 0 or 1
	42	- Note: Symbols like SE0, SE1, and the J that's part of EOP don't yield 'BIT'.
	43	'''
	44
	45	# Low-/full-speed symbols.
	46	# Note: Low-speed J and K are inverted compared to the full-speed J and K!
	47	symbols = {
	48	'low-speed': {
	49	# (<dp>, <dm>): <symbol/state>
	50	(0, 0): 'SE0',
	51	(1, 0): 'K',
	52	(0, 1): 'J',
	53	(1, 1): 'SE1',
	54	},
	55	'full-speed': {
	56	# (<dp>, <dm>): <symbol/state>
	57	(0, 0): 'SE0',
	58	(1, 0): 'J',
	59	(0, 1): 'K',
	60	(1, 1): 'SE1',
	61	},
	62	}
	63
	64	bitrates = {
	65	'low-speed': 1500000, # 1.5Mb/s (+/- 1.5%)
	66	'full-speed': 12000000, # 12Mb/s (+/- 0.25%)
	67	}
	68
	69	sym_idx = {
	70	'J': 0,
	71	'K': 1,
	72	'SE0': 2,
	73	'SE1': 3,
	74	}
	75
	76	class SamplerateError(Exception):
	77	pass
	78
	79	class Decoder(srd.Decoder):
	80	api_version = 2
	81	id = 'usb_signalling'
	82	name = 'USB signalling'
	83	longname = 'Universal Serial Bus (LS/FS) signalling'
	84	desc = 'USB (low-speed and full-speed) signalling protocol.'
	85	license = 'gplv2+'
	86	inputs = ['logic']
	87	outputs = ['usb_signalling']
	88	channels = (
	89	{'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
	90	{'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
	91	)
	92	options = (
	93	{'id': 'signalling', 'desc': 'Signalling',
	94	'default': 'full-speed', 'values': ('full-speed', 'low-speed')},
	95	)
	96	annotations = (
	97	('sym-j', 'J symbol'),
	98	('sym-k', 'K symbol'),
	99	('sym-se0', 'SE0 symbol'),
	100	('sym-se1', 'SE1 symbol'),
	101	('sop', 'Start of packet (SOP)'),
	102	('eop', 'End of packet (EOP)'),
	103	('bit', 'Bit'),
	104	('stuffbit', 'Stuff bit'),
	105	)
	106	annotation_rows = (
	107	('bits', 'Bits', (4, 5, 6, 7)),
	108	('symbols', 'Symbols', (0, 1, 2, 3)),
	109	)
	110
	111	def __init__(self):
	112	self.samplerate = None
	113	self.oldsym = 'J' # The "idle" state is J.
	114	self.ss_sop = None
	115	self.ss_block = None
	116	self.samplenum = 0
	117	self.syms = []
	118	self.bitrate = None
	119	self.bitwidth = None
	120	self.samplepos = None
	121	self.samplenum_target = None
	122	self.samplenum_edge = None
	123	self.oldpins = None
	124	self.edgepins = None
	125	self.consecutive_ones = 0
	126	self.state = 'IDLE'
	127
	128	def start(self):
	129	self.out_python = self.register(srd.OUTPUT_PYTHON)
	130	self.out_ann = self.register(srd.OUTPUT_ANN)
	131
	132	def metadata(self, key, value):
	133	if key == srd.SRD_CONF_SAMPLERATE:
	134	self.samplerate = value
	135	self.bitrate = bitrates[self.options['signalling']]
	136	self.bitwidth = float(self.samplerate) / float(self.bitrate)
	137	self.halfbit = int(self.bitwidth / 2)
	138
	139	def putpx(self, data):
	140	self.put(self.samplenum, self.samplenum, self.out_python, data)
	141
	142	def putx(self, data):
	143	self.put(self.samplenum, self.samplenum, self.out_ann, data)
	144
	145	def putpm(self, data):
	146	s, h = self.samplenum, self.halfbit
	147	self.put(self.ss_block - h, s + h, self.out_python, data)
	148
	149	def putm(self, data):
	150	s, h = self.samplenum, self.halfbit
	151	self.put(self.ss_block - h, s + h, self.out_ann, data)
	152
	153	def putpb(self, data):
	154	s, h = self.samplenum, self.halfbit
	155	self.put(self.samplenum_edge, s + h, self.out_python, data)
	156
	157	def putb(self, data):
	158	s, h = self.samplenum, self.halfbit
	159	self.put(self.samplenum_edge, s + h, self.out_ann, data)
	160
	161	def set_new_target_samplenum(self):
	162	self.samplepos += self.bitwidth;
	163	self.samplenum_target = int(self.samplepos)
	164	self.samplenum_edge = int(self.samplepos - (self.bitwidth / 2))
	165
	166	def wait_for_sop(self, sym):
	167	# Wait for a Start of Packet (SOP), i.e. a J->K symbol change.
	168	if sym != 'K':
	169	self.oldsym = sym
	170	return
	171	self.ss_sop = self.samplenum
	172	self.samplepos = self.ss_sop - (self.bitwidth / 2) + 0.5
	173	self.set_new_target_samplenum()
	174	self.putpx(['SOP', None])
	175	self.putx([4, ['SOP', 'S']])
	176	self.state = 'GET BIT'
	177
	178	def handle_bit(self, sym, b):
	179	if self.consecutive_ones == 6 and b == '0':
	180	# Stuff bit.
	181	self.putpb(['STUFF BIT', None])
	182	self.putb([7, ['Stuff bit: %s' % b, 'SB: %s' % b, '%s' % b]])
	183	self.putb([sym_idx[sym], ['%s' % sym]])
	184	self.consecutive_ones = 0
	185	else:
	186	# Normal bit (not a stuff bit).
	187	self.putpb(['BIT', b])
	188	self.putb([6, ['%s' % b]])
	189	self.putb([sym_idx[sym], ['%s' % sym]])
	190	if b == '1':
	191	self.consecutive_ones += 1
	192	else:
	193	self.consecutive_ones = 0
	194
	195	def get_eop(self, sym):
	196	# EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J.
	197	self.syms.append(sym)
	198	self.putpb(['SYM', sym])
	199	self.putb([sym_idx[sym], ['%s' % sym, '%s' % sym[0]]])
	200	self.set_new_target_samplenum()
	201	self.oldsym = sym
	202	if self.syms[-2:] == ['SE0', 'J']:
	203	# Got an EOP.
	204	self.putpm(['EOP', None])
	205	self.putm([5, ['EOP', 'E']])
	206	self.syms, self.state = [], 'IDLE'
	207	self.consecutive_ones = 0
	208	self.bitwidth = float(self.samplerate) / float(self.bitrate)
	209
	210	def get_bit(self, sym):
	211	if sym == 'SE0':
	212	# Start of an EOP. Change state, run get_eop() for this bit.
	213	self.state = 'GET EOP'
	214	self.ss_block = self.samplenum
	215	self.get_eop(sym)
	216	return
	217	self.syms.append(sym)
	218	self.putpb(['SYM', sym])
	219	b = '0' if self.oldsym != sym else '1'
	220	if (self.oldsym != sym):
	221	# edge
	222	edgesym = symbols[self.options['signalling']][tuple(self.edgepins)]
	223	if (edgesym not in ('SE0', 'SE1')):
	224	if (edgesym == sym):
	225	self.bitwidth = self.bitwidth - (0.001 * self.bitwidth)
	226	self.samplepos = self.samplepos - (0.01 * self.bitwidth)
	227	else:
	228	self.bitwidth = self.bitwidth + (0.001 * self.bitwidth)
	229	self.samplepos = self.samplepos + (0.01 * self.bitwidth)
	230	self.handle_bit(sym, b)
	231	self.set_new_target_samplenum()
	232	self.oldsym = sym
	233
	234	def decode(self, ss, es, data):
	235	if not self.samplerate:
	236	raise SamplerateError('Cannot decode without samplerate.')
	237	for (self.samplenum, pins) in data:
	238	# State machine.
	239	if self.state == 'IDLE':
	240	# Ignore identical samples early on (for performance reasons).
	241	if self.oldpins == pins:
	242	continue
	243	self.oldpins = pins
	244	sym = symbols[self.options['signalling']][tuple(pins)]
	245	self.wait_for_sop(sym)
	246	self.edgepins = pins
	247	elif self.state in ('GET BIT', 'GET EOP'):
	248	# Wait until we're in the middle of the desired bit.
	249	if self.samplenum == self.samplenum_edge:
	250	self.edgepins = pins
	251	if self.samplenum < self.samplenum_target:
	252	continue
	253	sym = symbols[self.options['signalling']][tuple(pins)]
	254	if self.state == 'GET BIT':
	255	self.get_bit(sym)
	256	elif self.state == 'GET EOP':
	257	self.get_eop(sym)