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srd: All PDs: Various fixes, cosmetics.
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1##
2## This file is part of the sigrok project.
3##
4## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; either version 2 of the License, or
9## (at your option) any later version.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
17## along with this program; if not, write to the Free Software
18## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19##
20
21#
22# USB Full-speed protocol decoder
23#
24# Full-speed USB signalling consists of two signal lines, both driven at 3.3V
25# logic levels. The signals are DP (D+) and DM (D-), and normally operate in
26# differential mode.
27# The state where DP=1,DM=0 is J, the state DP=0,DM=1 is K.
28# A state SE0 is defined where DP=DM=0. This common mode signal is used to
29# signal a reset or end of packet.
30#
31# Data transmitted on the USB is encoded with NRZI. A transition from J to K
32# or vice-versa indicates a logic 0, while no transition indicates a logic 1.
33# If 6 ones are transmitted consecutively, a zero is inserted to force a
34# transition. This is known as bit stuffing. Data is transferred at a rate
35# of 12Mbit/s. The SE0 transmitted to signal an end-of-packet is two bit
36# intervals long.
37#
38# Details:
39# https://en.wikipedia.org/wiki/USB
40# http://www.usb.org/developers/docs/
41#
42
43import sigrokdecode as srd
44
45# States
46SE0, J, K, SE1 = 0, 1, 2, 3
47
48# ...
49syms = {
50 (0, 0): SE0,
51 (1, 0): J,
52 (0, 1): K,
53 (1, 1): SE1,
54}
55
56# ...
57pids = {
58 '10000111': 'OUT', # Tokens
59 '10010110': 'IN',
60 '10100101': 'SOF',
61 '10110100': 'SETUP',
62 '11000011': 'DATA0', # Data
63 '11010010': 'DATA1',
64 '01001011': 'ACK', # Handshake
65 '01011010': 'NAK',
66 '01111000': 'STALL',
67 '01101001': 'NYET',
68}
69
70def bitstr_to_num(bitstr):
71 if not bitstr:
72 return 0
73 l = list(bitstr)
74 l.reverse()
75 return int(''.join(l), 2)
76
77def packet_decode(packet):
78 sync = packet[:8]
79 pid = packet[8:16]
80 pid = pids.get(pid, pid)
81
82 # Remove CRC.
83 if pid in ('OUT', 'IN', 'SOF', 'SETUP'):
84 data = packet[16:-5]
85 if pid == 'SOF':
86 data = str(bitstr_to_num(data))
87 else:
88 dev = bitstr_to_num(data[:7])
89 ep = bitstr_to_num(data[7:])
90 data = 'DEV %d EP %d' % (dev, ep)
91
92 elif pid in ('DATA0', 'DATA1'):
93 data = packet[16:-16]
94 tmp = ''
95 while data:
96 tmp += '%02x ' % bitstr_to_num(data[:8])
97 data = data[8:]
98 data = tmp
99 else:
100 data = packet[16:]
101
102 if sync != '00000001':
103 return 'SYNC INVALID!'
104
105 return pid + ' ' + data
106
107class Decoder(srd.Decoder):
108 api_version = 1
109 id = 'usb'
110 name = 'USB'
111 longname = 'Universal Serial Bus'
112 desc = 'Universal Serial Bus'
113 longdesc = '...longdesc...'
114 license = 'gplv2+'
115 inputs = ['logic']
116 outputs = ['usb']
117 probes = [
118 {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
119 {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
120 ]
121 extra_probes = []
122 options = {}
123 annotations = [
124 ['TODO', 'TODO']
125 ]
126
127 def __init__(self):
128 pass
129
130 def start(self, metadata):
131 self.rate = metadata['samplerate']
132
133 # self.out_proto = self.add(srd.OUTPUT_PROTO, 'usb')
134 self.out_ann = self.add(srd.OUTPUT_ANN, 'usb')
135
136 if self.rate < 48000000:
137 raise Exception('Sample rate (%d) not sufficient for USB '
138 'decoding, need at least 48MHz' % self.rate)
139
140 # Initialise decoder state.
141 self.sym = J
142 self.scount = 0
143 self.packet = ''
144
145 def report(self):
146 pass
147
148 def decode(self, ss, es, data):
149 for (samplenum, (dm, dp)) in data:
150
151 self.scount += 1
152
153 sym = syms[dp, dm]
154
155 # ...
156 if sym == self.sym:
157 continue
158
159 if self.scount == 1:
160 # We ignore single sample width pulses.
161 # I sometimes get these with the OLS.
162 self.sym = sym
163 self.scount = 0
164 continue
165
166 # How many bits since the last transition?
167 if self.packet != '' or self.sym != J:
168 bitcount = int((self.scount - 1) * 12000000 / self.rate)
169 else:
170 bitcount = 0
171
172 if self.sym == SE0:
173 if bitcount == 1:
174 # End-Of-Packet (EOP)
175 self.put(0, 0, self.out_ann,
176 [0, [packet_decode(self.packet), self.packet]])
177 else:
178 # Longer than EOP, assume reset.
179 self.put(0, 0, self.out_ann, [0, ['RESET']])
180 self.scount = 0
181 self.sym = sym
182 self.packet = ''
183 continue
184
185 # Add bits to the packet string.
186 self.packet += '1' * bitcount
187
188 # Handle bit stuffing.
189 if bitcount < 6 and sym != SE0:
190 self.packet += '0'
191 elif bitcount > 6:
192 self.put(0, 0, self.out_ann, [0, ['BIT STUFF ERROR']])
193
194 self.scount = 0
195 self.sym = sym
196