]>
Commit | Line | Data |
---|---|---|
1 | ## | |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2012-2015 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | import sigrokdecode as srd | |
22 | ||
23 | dacs = { | |
24 | 0: 'DACA', | |
25 | 1: 'DACB', | |
26 | 2: 'DACC', | |
27 | 3: 'DACD', | |
28 | } | |
29 | ||
30 | class Decoder(srd.Decoder): | |
31 | api_version = 2 | |
32 | id = 'tlc5620' | |
33 | name = 'TI TLC5620' | |
34 | longname = 'Texas Instruments TLC5620' | |
35 | desc = 'Texas Instruments TLC5620 8-bit quad DAC.' | |
36 | license = 'gplv2+' | |
37 | inputs = ['logic'] | |
38 | outputs = ['tlc5620'] | |
39 | channels = ( | |
40 | {'id': 'clk', 'name': 'CLK', 'desc': 'Serial interface clock'}, | |
41 | {'id': 'data', 'name': 'DATA', 'desc': 'Serial interface data'}, | |
42 | ) | |
43 | optional_channels = ( | |
44 | {'id': 'load', 'name': 'LOAD', 'desc': 'Serial interface load control'}, | |
45 | {'id': 'ldac', 'name': 'LDAC', 'desc': 'Load DAC'}, | |
46 | ) | |
47 | annotations = ( | |
48 | ('dac-select', 'DAC select'), | |
49 | ('gain', 'Gain'), | |
50 | ('value', 'DAC value'), | |
51 | ('data-latch', 'Data latch point'), | |
52 | ('ldac-fall', 'LDAC falling edge'), | |
53 | ('bit', 'Bit'), | |
54 | ('operation', 'Operation'), | |
55 | ) | |
56 | annotation_rows = ( | |
57 | ('bits', 'Bits', (5,)), | |
58 | ('fields', 'Fields', (0, 1, 2)), | |
59 | ('operations', 'Operations', (6,)), | |
60 | ('events', 'Events', (3, 4)), | |
61 | ) | |
62 | ||
63 | def __init__(self, **kwargs): | |
64 | self.oldpins = self.oldclk = self.oldload = self.oldldac = None | |
65 | self.datapin = None | |
66 | self.bits = [] | |
67 | self.ss_dac = self.es_dac = 0 | |
68 | self.ss_gain = self.es_gain = 0 | |
69 | self.ss_value = self.es_value = 0 | |
70 | self.dac_select = self.gain = self.dac_value = None | |
71 | ||
72 | def start(self): | |
73 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
74 | ||
75 | def handle_11bits(self): | |
76 | s = ''.join(str(i[0]) for i in self.bits[:2]) | |
77 | self.dac_select = s = dacs[int(s, 2)] | |
78 | self.put(self.ss_dac, self.es_dac, self.out_ann, | |
79 | [0, ['DAC select: %s' % s, 'DAC sel: %s' % s, | |
80 | 'DAC: %s' % s, 'D: %s' % s, s, s[3]]]) | |
81 | ||
82 | self.gain = g = 1 + self.bits[2][0] | |
83 | self.put(self.ss_gain, self.es_gain, self.out_ann, | |
84 | [1, ['Gain: x%d' % g, 'G: x%d' % g, 'x%d' % g]]) | |
85 | ||
86 | s = ''.join(str(i[0]) for i in self.bits[3:]) | |
87 | self.dac_value = v = int(s, 2) | |
88 | self.put(self.ss_value, self.es_value, self.out_ann, | |
89 | [2, ['DAC value: %d' % v, 'Value: %d' % v, 'Val: %d' % v, | |
90 | 'V: %d' % v, '%d' % v]]) | |
91 | ||
92 | # Emit an annotation for each bit. | |
93 | for i in range(1, 11): | |
94 | self.put(self.bits[i - 1][1], self.bits[i][1], self.out_ann, | |
95 | [5, [str(self.bits[i - 1][0])]]) | |
96 | self.put(self.bits[10][1], self.bits[10][1] + self.clock_width, | |
97 | self.out_ann, [5, [str(self.bits[10][0])]]) | |
98 | ||
99 | def handle_falling_edge_load(self): | |
100 | s, v, g = self.dac_select, self.dac_value, self.gain | |
101 | self.put(self.samplenum, self.samplenum, self.out_ann, | |
102 | [3, ['Falling edge on LOAD', 'LOAD fall', 'F']]) | |
103 | self.put(self.ss_dac, self.es_value, self.out_ann, | |
104 | [6, ['Setting %s value to %d (x%d gain)' % (s, v, g), | |
105 | '%s=%d (x%d gain)' % (s, v, g)]]) | |
106 | ||
107 | def handle_falling_edge_ldac(self): | |
108 | self.put(self.samplenum, self.samplenum, self.out_ann, | |
109 | [4, ['Falling edge on LDAC', 'LDAC fall', 'LDAC', 'L']]) | |
110 | ||
111 | def handle_new_dac_bit(self): | |
112 | self.bits.append([self.datapin, self.samplenum]) | |
113 | ||
114 | # Wait until we have read 11 bits, then parse them. | |
115 | l, s = len(self.bits), self.samplenum | |
116 | if l == 1: | |
117 | self.ss_dac = s | |
118 | elif l == 3: | |
119 | self.es_dac = self.ss_gain = s | |
120 | elif l == 4: | |
121 | self.es_gain = self.ss_value = s | |
122 | self.clock_width = self.es_gain - self.ss_gain | |
123 | elif l == 11: | |
124 | self.es_value = s + self.clock_width # Guessed. | |
125 | self.handle_11bits() | |
126 | self.bits = [] | |
127 | ||
128 | def decode(self, ss, es, data): | |
129 | for (self.samplenum, pins) in data: | |
130 | ||
131 | # Ignore identical samples early on (for performance reasons). | |
132 | if self.oldpins == pins: | |
133 | continue | |
134 | self.oldpins, (clk, self.datapin, load, ldac) = pins, pins | |
135 | ||
136 | # DATA is shifted in the DAC on the falling CLK edge (MSB-first). | |
137 | # A falling edge of LOAD will latch the data. | |
138 | ||
139 | if self.oldload == 1 and load == 0: | |
140 | self.handle_falling_edge_load() | |
141 | if self.oldldac == 1 and ldac == 0: | |
142 | self.handle_falling_edge_ldac() | |
143 | if self.oldclk == 1 and clk == 0: | |
144 | self.handle_new_dac_bit() | |
145 | ||
146 | self.oldclk = clk | |
147 | self.oldload = load | |
148 | self.oldldac = ldac |