[libsigrokdecode.git] / decoders / spiflash / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2011-2015 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

import sigrokdecode as srd
from .lists import *

def cmd_annotation_classes():
    return tuple([tuple([cmd[0].lower(), cmd[1]]) for cmd in cmds.values()])

def decode_dual_bytes(sio0, sio1):
    # Given a byte in SIO0 (MOSI) of even bits and a byte in
    # SIO1 (MISO) of odd bits, return a tuple of two bytes.
    def combine_byte(even, odd):
        result = 0
        for bit in range(4):
            if even & (1 << bit):
                result |= 1 << (bit*2)
            if odd & (1 << bit):
                result |= 1 << ((bit*2) + 1)
        return result
    return (combine_byte(sio0 >> 4, sio1 >> 4), combine_byte(sio0, sio1))

def decode_status_reg(data):
    # TODO: Additional per-bit(s) self.put() calls with correct start/end.

    # Bits[0:0]: WIP (write in progress)
    s = 'W' if (data & (1 << 0)) else 'No w'
    ret = '%srite operation in progress.\n' % s

    # Bits[1:1]: WEL (write enable latch)
    s = '' if (data & (1 << 1)) else 'not '
    ret += 'Internal write enable latch is %sset.\n' % s

    # Bits[5:2]: Block protect bits
    # TODO: More detailed decoding (chip-dependent).
    ret += 'Block protection bits (BP3-BP0): 0x%x.\n' % ((data & 0x3c) >> 2)

    # Bits[6:6]: Continuously program mode (CP mode)
    s = '' if (data & (1 << 6)) else 'not '
    ret += 'Device is %sin continuously program mode (CP mode).\n' % s

    # Bits[7:7]: SRWD (status register write disable)
    s = 'not ' if (data & (1 << 7)) else ''
    ret += 'Status register writes are %sallowed.\n' % s

    return ret

class Decoder(srd.Decoder):
    api_version = 2
    id = 'spiflash'
    name = 'SPI flash'
    longname = 'SPI flash chips'
    desc = 'xx25 series SPI (NOR) flash chip protocol.'
    license = 'gplv2+'
    inputs = ['spi']
    outputs = ['spiflash']
    annotations = cmd_annotation_classes() + (
        ('bits', 'Bits'),
        ('bits2', 'Bits2'),
        ('warnings', 'Warnings'),
    )
    annotation_rows = (
        ('bits', 'Bits', (24, 25)),
        ('commands', 'Commands', tuple(range(23 + 1))),
        ('warnings', 'Warnings', (26,)),
    )
    options = (
        {'id': 'chip', 'desc': 'Chip', 'default': tuple(chips.keys())[0],
            'values': tuple(chips.keys())},
        {'id': 'format', 'desc': 'Data format', 'default': 'hex',
            'values': ('hex', 'ascii')},
    )

    def __init__(self):
        self.on_end_transaction = None
        self.end_current_transaction()

        # Build dict mapping command keys to handler functions. Each
        # command in 'cmds' (defined in lists.py) has a matching
        # handler self.handle_<shortname>.
        def get_handler(cmd):
            s = 'handle_%s' % cmds[cmd][0].lower().replace('/', '_')
            return getattr(self, s)
        self.cmd_handlers = dict((cmd, get_handler(cmd)) for cmd in cmds.keys())

    def end_current_transaction(self):
        if self.on_end_transaction is not None: # Callback for CS# transition.
            self.on_end_transaction()
            self.on_end_transaction = None
        self.state = None
        self.cmdstate = 1
        self.addr = 0
        self.data = []

    def start(self):
        self.out_ann = self.register(srd.OUTPUT_ANN)
        self.chip = chips[self.options['chip']]

    def putx(self, data):
        # Simplification, most annotations span exactly one SPI byte/packet.
        self.put(self.ss, self.es, self.out_ann, data)

    def putb(self, data):
        self.put(self.ss_block, self.es_block, self.out_ann, data)

    def handle_wren(self, mosi, miso):
        self.putx([0, ['Command: %s' % cmds[self.state][1]]])
        self.state = None

    def handle_wrdi(self, mosi, miso):
        pass # TODO

    # TODO: Check/display device ID / name
    def handle_rdid(self, mosi, miso):
        if self.cmdstate == 1:
            # Byte 1: Master sends command ID.
            self.ss_block = self.ss
            self.putx([2, ['Command: %s' % cmds[self.state][1]]])
        elif self.cmdstate == 2:
            # Byte 2: Slave sends the JEDEC manufacturer ID.
            self.putx([2, ['Manufacturer ID: 0x%02x' % miso]])
        elif self.cmdstate == 3:
            # Byte 3: Slave sends the memory type (0x20 for this chip).
            self.putx([2, ['Memory type: 0x%02x' % miso]])
        elif self.cmdstate == 4:
            # Byte 4: Slave sends the device ID.
            self.device_id = miso
            self.putx([2, ['Device ID: 0x%02x' % miso]])

        if self.cmdstate == 4:
            # TODO: Check self.device_id is valid & exists in device_names.
            # TODO: Same device ID? Check!
            d = 'Device: Macronix %s' % device_name[self.device_id]
            self.put(self.ss_block, self.es, self.out_ann, [0, [d]])
            self.state = None
        else:
            self.cmdstate += 1

    def handle_rdsr(self, mosi, miso):
        # Read status register: Master asserts CS#, sends RDSR command,
        # reads status register byte. If CS# is kept asserted, the status
        # register can be read continuously / multiple times in a row.
        # When done, the master de-asserts CS# again.
        if self.cmdstate == 1:
            # Byte 1: Master sends command ID.
            self.putx([3, ['Command: %s' % cmds[self.state][1]]])
        elif self.cmdstate >= 2:
            # Bytes 2-x: Slave sends status register as long as master clocks.
            self.putx([24, ['Status register: 0x%02x' % miso]])
            self.putx([25, [decode_status_reg(miso)]])

        self.cmdstate += 1

    def handle_wrsr(self, mosi, miso):
        pass # TODO

    def handle_read(self, mosi, miso):
        # Read data bytes: Master asserts CS#, sends READ command, sends
        # 3-byte address, reads >= 1 data bytes, de-asserts CS#.
        if self.cmdstate == 1:
            # Byte 1: Master sends command ID.
            self.putx([5, ['Command: %s' % cmds[self.state][1]]])
        elif self.cmdstate in (2, 3, 4):
            # Bytes 2/3/4: Master sends read address (24bits, MSB-first).
            self.addr |= (mosi << ((4 - self.cmdstate) * 8))
            # self.putx([0, ['Read address, byte %d: 0x%02x' % \
            #                (4 - self.cmdstate, mosi)]])
            if self.cmdstate == 4:
                self.putx([24, ['Read address: 0x%06x' % self.addr]])
                self.addr = 0
        elif self.cmdstate >= 5:
            # Bytes 5-x: Master reads data bytes (until CS# de-asserted).
            if self.cmdstate == 5:
                self.ss_block = self.ss
                self.on_end_transaction = lambda: self.output_data_block('Read')
            self.data.append(miso)

        self.cmdstate += 1

    def handle_fast_read(self, mosi, miso):
        # Fast read: Master asserts CS#, sends FAST READ command, sends
        # 3-byte address + 1 dummy byte, reads >= 1 data bytes, de-asserts CS#.
        if self.cmdstate == 1:
            # Byte 1: Master sends command ID.
            self.putx([5, ['Command: %s' % cmds[self.state][1]]])
        elif self.cmdstate in (2, 3, 4):
            # Bytes 2/3/4: Master sends read address (24bits, MSB-first).
            self.putx([24, ['AD%d: 0x%02x' % (self.cmdstate - 1, mosi)]])
            if self.cmdstate == 2:
                self.ss_block = self.ss
            self.addr |= (mosi << ((4 - self.cmdstate) * 8))
        elif self.cmdstate == 5:
            self.putx([24, ['Dummy byte: 0x%02x' % mosi]])
            self.es_block = self.es
            self.putb([5, ['Read address: 0x%06x' % self.addr]])
            self.addr = 0
        elif self.cmdstate >= 6:
            # Bytes 6-x: Master reads data bytes (until CS# de-asserted).
            if self.cmdstate == 6:
                self.ss_block = self.ss
                self.on_end_transaction = lambda: self.output_data_block('Read')
            self.data.append(miso)

        self.cmdstate += 1

    def handle_2read(self, mosi, miso):
        # Fast read dual I/O: Same as fast read, but all data
        # after the command is sent via two I/O pins.
        # MOSI = SIO0 = even bits, MISO = SIO1 = odd bits.
        # Recombine the bytes and pass them up to the handle_fast_read command.
        if self.cmdstate == 1:
            # Byte 1: Master sends command ID.
            self.putx([5, ['Command: %s' % cmds[self.state][1]]])
            self.cmdstate = 2
        else:
            # Dual I/O mode.
            a, b = decode_dual_bytes(mosi, miso)
            # Pass same byte in as both MISO & MOSI, parser state determines
            # which one it cares about.
            self.handle_fast_read(a, a)
            self.handle_fast_read(b, b)

    # TODO: Warn/abort if we don't see the necessary amount of bytes.
    # TODO: Warn if WREN was not seen before.
    def handle_se(self, mosi, miso):
        if self.cmdstate == 1:
            # Byte 1: Master sends command ID.
            self.addr = 0
            self.ss_block = self.ss
            self.putx([8, ['Command: %s' % cmds[self.state][1]]])
        elif self.cmdstate in (2, 3, 4):
            # Bytes 2/3/4: Master sends sector address (24bits, MSB-first).
            self.addr |= (mosi << ((4 - self.cmdstate) * 8))
            # self.putx([0, ['Sector address, byte %d: 0x%02x' % \
            #                (4 - self.cmdstate, mosi)]])

        if self.cmdstate == 4:
            d = 'Erase sector %d (0x%06x)' % (self.addr, self.addr)
            self.put(self.ss_block, self.es, self.out_ann, [24, [d]])
            # TODO: Max. size depends on chip, check that too if possible.
            if self.addr % 4096 != 0:
                # Sector addresses must be 4K-aligned (same for all 3 chips).
                d = 'Warning: Invalid sector address!'
                self.put(self.ss_block, self.es, self.out_ann, [101, [d]])
            self.state = None
        else:
            self.cmdstate += 1

    def handle_be(self, mosi, miso):
        pass # TODO

    def handle_ce(self, mosi, miso):
        pass # TODO

    def handle_ce2(self, mosi, miso):
        pass # TODO

    def handle_pp(self, mosi, miso):
        # Page program: Master asserts CS#, sends PP command, sends 3-byte
        # page address, sends >= 1 data bytes, de-asserts CS#.
        if self.cmdstate == 1:
            # Byte 1: Master sends command ID.
            self.putx([12, ['Command: %s' % cmds[self.state][1]]])
        elif self.cmdstate in (2, 3, 4):
            # Bytes 2/3/4: Master sends page address (24bits, MSB-first).
            self.addr |= (mosi << ((4 - self.cmdstate) * 8))
            # self.putx([0, ['Page address, byte %d: 0x%02x' % \
            #                (4 - self.cmdstate, mosi)]])
            if self.cmdstate == 4:
                self.putx([24, ['Page address: 0x%06x' % self.addr]])
                self.addr = 0
        elif self.cmdstate >= 5:
            # Bytes 5-x: Master sends data bytes (until CS# de-asserted).
            if self.cmdstate == 5:
                self.ss_block = self.ss
                self.on_end_transaction = lambda: self.output_data_block('Page data')
            self.data.append(mosi)

        self.cmdstate += 1

    def handle_cp(self, mosi, miso):
        pass # TODO

    def handle_dp(self, mosi, miso):
        pass # TODO

    def handle_rdp_res(self, mosi, miso):
        pass # TODO

    def handle_rems(self, mosi, miso):
        if self.cmdstate == 1:
            # Byte 1: Master sends command ID.
            self.ss_block = self.ss
            self.putx([16, ['Command: %s' % cmds[self.state][1]]])
        elif self.cmdstate in (2, 3):
            # Bytes 2/3: Master sends two dummy bytes.
            # TODO: Check dummy bytes? Check reply from device?
            self.putx([24, ['Dummy byte: %s' % mosi]])
        elif self.cmdstate == 4:
            # Byte 4: Master sends 0x00 or 0x01.
            # 0x00: Master wants manufacturer ID as first reply byte.
            # 0x01: Master wants device ID as first reply byte.
            self.manufacturer_id_first = True if (mosi == 0x00) else False
            d = 'manufacturer' if (mosi == 0x00) else 'device'
            self.putx([24, ['Master wants %s ID first' % d]])
        elif self.cmdstate == 5:
            # Byte 5: Slave sends manufacturer ID (or device ID).
            self.ids = [miso]
            d = 'Manufacturer' if self.manufacturer_id_first else 'Device'
            self.putx([24, ['%s ID' % d]])
        elif self.cmdstate == 6:
            # Byte 6: Slave sends device ID (or manufacturer ID).
            self.ids.append(miso)
            d = 'Manufacturer' if self.manufacturer_id_first else 'Device'
            self.putx([24, ['%s ID' % d]])

        if self.cmdstate == 6:
            id = self.ids[1] if self.manufacturer_id_first else self.ids[0]
            self.putx([24, ['Device: Macronix %s' % device_name[id]]])
            self.state = None
        else:
            self.cmdstate += 1

    def handle_rems2(self, mosi, miso):
        pass # TODO

    def handle_enso(self, mosi, miso):
        pass # TODO

    def handle_exso(self, mosi, miso):
        pass # TODO

    def handle_rdscur(self, mosi, miso):
        pass # TODO

    def handle_wrscur(self, mosi, miso):
        pass # TODO

    def handle_esry(self, mosi, miso):
        pass # TODO

    def handle_dsry(self, mosi, miso):
        pass # TODO

    def output_data_block(self, label):
        # Print accumulated block of data
        # (called on CS# de-assert via self.on_end_transaction callback).
        self.es_block = self.es # Ends on the CS# de-assert sample.
        if self.options['format'] == 'hex':
            s = ' '.join([('%02x' % b) for b in self.data])
        else:
            s = ''.join(map(chr, self.data))
        self.putb([25, ['%s %d bytes: %s' % (label, len(self.data), s)]])

    def decode(self, ss, es, data):
        ptype, mosi, miso = data

        self.ss, self.es = ss, es

        if ptype == 'CS-CHANGE':
            self.end_current_transaction()

        if ptype != 'DATA':
            return

        # If we encountered a known chip command, enter the resp. state.
        if self.state is None:
            self.state = mosi
            self.cmdstate = 1

        # Handle commands.
        try:
            self.cmd_handlers[self.state](mosi, miso)
        except KeyError:
            self.putx([24, ['Unknown command: 0x%02x' % mosi]])
            self.state = None
Commit	Line	Data
	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2011-2015 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
	21	import sigrokdecode as srd
	22	from .lists import *
	23
	24	def cmd_annotation_classes():
	25	return tuple([tuple([cmd[0].lower(), cmd[1]]) for cmd in cmds.values()])
	26
	27	def decode_dual_bytes(sio0, sio1):
	28	# Given a byte in SIO0 (MOSI) of even bits and a byte in
	29	# SIO1 (MISO) of odd bits, return a tuple of two bytes.
	30	def combine_byte(even, odd):
	31	result = 0
	32	for bit in range(4):
	33	if even & (1 << bit):
	34	result \|= 1 << (bit*2)
	35	if odd & (1 << bit):
	36	result \|= 1 << ((bit*2) + 1)
	37	return result
	38	return (combine_byte(sio0 >> 4, sio1 >> 4), combine_byte(sio0, sio1))
	39
	40	def decode_status_reg(data):
	41	# TODO: Additional per-bit(s) self.put() calls with correct start/end.
	42
	43	# Bits[0:0]: WIP (write in progress)
	44	s = 'W' if (data & (1 << 0)) else 'No w'
	45	ret = '%srite operation in progress.\n' % s
	46
	47	# Bits[1:1]: WEL (write enable latch)
	48	s = '' if (data & (1 << 1)) else 'not '
	49	ret += 'Internal write enable latch is %sset.\n' % s
	50
	51	# Bits[5:2]: Block protect bits
	52	# TODO: More detailed decoding (chip-dependent).
	53	ret += 'Block protection bits (BP3-BP0): 0x%x.\n' % ((data & 0x3c) >> 2)
	54
	55	# Bits[6:6]: Continuously program mode (CP mode)
	56	s = '' if (data & (1 << 6)) else 'not '
	57	ret += 'Device is %sin continuously program mode (CP mode).\n' % s
	58
	59	# Bits[7:7]: SRWD (status register write disable)
	60	s = 'not ' if (data & (1 << 7)) else ''
	61	ret += 'Status register writes are %sallowed.\n' % s
	62
	63	return ret
	64
	65	class Decoder(srd.Decoder):
	66	api_version = 2
	67	id = 'spiflash'
	68	name = 'SPI flash'
	69	longname = 'SPI flash chips'
	70	desc = 'xx25 series SPI (NOR) flash chip protocol.'
	71	license = 'gplv2+'
	72	inputs = ['spi']
	73	outputs = ['spiflash']
	74	annotations = cmd_annotation_classes() + (
	75	('bits', 'Bits'),
	76	('bits2', 'Bits2'),
	77	('warnings', 'Warnings'),
	78	)
	79	annotation_rows = (
	80	('bits', 'Bits', (24, 25)),
	81	('commands', 'Commands', tuple(range(23 + 1))),
	82	('warnings', 'Warnings', (26,)),
	83	)
	84	options = (
	85	{'id': 'chip', 'desc': 'Chip', 'default': tuple(chips.keys())[0],
	86	'values': tuple(chips.keys())},
	87	{'id': 'format', 'desc': 'Data format', 'default': 'hex',
	88	'values': ('hex', 'ascii')},
	89	)
	90
	91	def __init__(self):
	92	self.on_end_transaction = None
	93	self.end_current_transaction()
	94
	95	# Build dict mapping command keys to handler functions. Each
	96	# command in 'cmds' (defined in lists.py) has a matching
	97	# handler self.handle_<shortname>.
	98	def get_handler(cmd):
	99	s = 'handle_%s' % cmds[cmd][0].lower().replace('/', '_')
	100	return getattr(self, s)
	101	self.cmd_handlers = dict((cmd, get_handler(cmd)) for cmd in cmds.keys())
	102
	103	def end_current_transaction(self):
	104	if self.on_end_transaction is not None: # Callback for CS# transition.
	105	self.on_end_transaction()
	106	self.on_end_transaction = None
	107	self.state = None
	108	self.cmdstate = 1
	109	self.addr = 0
	110	self.data = []
	111
	112	def start(self):
	113	self.out_ann = self.register(srd.OUTPUT_ANN)
	114	self.chip = chips[self.options['chip']]
	115
	116	def putx(self, data):
	117	# Simplification, most annotations span exactly one SPI byte/packet.
	118	self.put(self.ss, self.es, self.out_ann, data)
	119
	120	def putb(self, data):
	121	self.put(self.ss_block, self.es_block, self.out_ann, data)
	122
	123	def handle_wren(self, mosi, miso):
	124	self.putx([0, ['Command: %s' % cmds[self.state][1]]])
	125	self.state = None
	126
	127	def handle_wrdi(self, mosi, miso):
	128	pass # TODO
	129
	130	# TODO: Check/display device ID / name
	131	def handle_rdid(self, mosi, miso):
	132	if self.cmdstate == 1:
	133	# Byte 1: Master sends command ID.
	134	self.ss_block = self.ss
	135	self.putx([2, ['Command: %s' % cmds[self.state][1]]])
	136	elif self.cmdstate == 2:
	137	# Byte 2: Slave sends the JEDEC manufacturer ID.
	138	self.putx([2, ['Manufacturer ID: 0x%02x' % miso]])
	139	elif self.cmdstate == 3:
	140	# Byte 3: Slave sends the memory type (0x20 for this chip).
	141	self.putx([2, ['Memory type: 0x%02x' % miso]])
	142	elif self.cmdstate == 4:
	143	# Byte 4: Slave sends the device ID.
	144	self.device_id = miso
	145	self.putx([2, ['Device ID: 0x%02x' % miso]])
	146
	147	if self.cmdstate == 4:
	148	# TODO: Check self.device_id is valid & exists in device_names.
	149	# TODO: Same device ID? Check!
	150	d = 'Device: Macronix %s' % device_name[self.device_id]
	151	self.put(self.ss_block, self.es, self.out_ann, [0, [d]])
	152	self.state = None
	153	else:
	154	self.cmdstate += 1
	155
	156	def handle_rdsr(self, mosi, miso):
	157	# Read status register: Master asserts CS#, sends RDSR command,
	158	# reads status register byte. If CS# is kept asserted, the status
	159	# register can be read continuously / multiple times in a row.
	160	# When done, the master de-asserts CS# again.
	161	if self.cmdstate == 1:
	162	# Byte 1: Master sends command ID.
	163	self.putx([3, ['Command: %s' % cmds[self.state][1]]])
	164	elif self.cmdstate >= 2:
	165	# Bytes 2-x: Slave sends status register as long as master clocks.
	166	self.putx([24, ['Status register: 0x%02x' % miso]])
	167	self.putx([25, [decode_status_reg(miso)]])
	168
	169	self.cmdstate += 1
	170
	171	def handle_wrsr(self, mosi, miso):
	172	pass # TODO
	173
	174	def handle_read(self, mosi, miso):
	175	# Read data bytes: Master asserts CS#, sends READ command, sends
	176	# 3-byte address, reads >= 1 data bytes, de-asserts CS#.
	177	if self.cmdstate == 1:
	178	# Byte 1: Master sends command ID.
	179	self.putx([5, ['Command: %s' % cmds[self.state][1]]])
	180	elif self.cmdstate in (2, 3, 4):
	181	# Bytes 2/3/4: Master sends read address (24bits, MSB-first).
	182	self.addr \|= (mosi << ((4 - self.cmdstate) * 8))
	183	# self.putx([0, ['Read address, byte %d: 0x%02x' % \
	184	# (4 - self.cmdstate, mosi)]])
	185	if self.cmdstate == 4:
	186	self.putx([24, ['Read address: 0x%06x' % self.addr]])
	187	self.addr = 0
	188	elif self.cmdstate >= 5:
	189	# Bytes 5-x: Master reads data bytes (until CS# de-asserted).
	190	if self.cmdstate == 5:
	191	self.ss_block = self.ss
	192	self.on_end_transaction = lambda: self.output_data_block('Read')
	193	self.data.append(miso)
	194
	195	self.cmdstate += 1
	196
	197	def handle_fast_read(self, mosi, miso):
	198	# Fast read: Master asserts CS#, sends FAST READ command, sends
	199	# 3-byte address + 1 dummy byte, reads >= 1 data bytes, de-asserts CS#.
	200	if self.cmdstate == 1:
	201	# Byte 1: Master sends command ID.
	202	self.putx([5, ['Command: %s' % cmds[self.state][1]]])
	203	elif self.cmdstate in (2, 3, 4):
	204	# Bytes 2/3/4: Master sends read address (24bits, MSB-first).
	205	self.putx([24, ['AD%d: 0x%02x' % (self.cmdstate - 1, mosi)]])
	206	if self.cmdstate == 2:
	207	self.ss_block = self.ss
	208	self.addr \|= (mosi << ((4 - self.cmdstate) * 8))
	209	elif self.cmdstate == 5:
	210	self.putx([24, ['Dummy byte: 0x%02x' % mosi]])
	211	self.es_block = self.es
	212	self.putb([5, ['Read address: 0x%06x' % self.addr]])
	213	self.addr = 0
	214	elif self.cmdstate >= 6:
	215	# Bytes 6-x: Master reads data bytes (until CS# de-asserted).
	216	if self.cmdstate == 6:
	217	self.ss_block = self.ss
	218	self.on_end_transaction = lambda: self.output_data_block('Read')
	219	self.data.append(miso)
	220
	221	self.cmdstate += 1
	222
	223	def handle_2read(self, mosi, miso):
	224	# Fast read dual I/O: Same as fast read, but all data
	225	# after the command is sent via two I/O pins.
	226	# MOSI = SIO0 = even bits, MISO = SIO1 = odd bits.
	227	# Recombine the bytes and pass them up to the handle_fast_read command.
	228	if self.cmdstate == 1:
	229	# Byte 1: Master sends command ID.
	230	self.putx([5, ['Command: %s' % cmds[self.state][1]]])
	231	self.cmdstate = 2
	232	else:
	233	# Dual I/O mode.
	234	a, b = decode_dual_bytes(mosi, miso)
	235	# Pass same byte in as both MISO & MOSI, parser state determines
	236	# which one it cares about.
	237	self.handle_fast_read(a, a)
	238	self.handle_fast_read(b, b)
	239
	240	# TODO: Warn/abort if we don't see the necessary amount of bytes.
	241	# TODO: Warn if WREN was not seen before.
	242	def handle_se(self, mosi, miso):
	243	if self.cmdstate == 1:
	244	# Byte 1: Master sends command ID.
	245	self.addr = 0
	246	self.ss_block = self.ss
	247	self.putx([8, ['Command: %s' % cmds[self.state][1]]])
	248	elif self.cmdstate in (2, 3, 4):
	249	# Bytes 2/3/4: Master sends sector address (24bits, MSB-first).
	250	self.addr \|= (mosi << ((4 - self.cmdstate) * 8))
	251	# self.putx([0, ['Sector address, byte %d: 0x%02x' % \
	252	# (4 - self.cmdstate, mosi)]])
	253
	254	if self.cmdstate == 4:
	255	d = 'Erase sector %d (0x%06x)' % (self.addr, self.addr)
	256	self.put(self.ss_block, self.es, self.out_ann, [24, [d]])
	257	# TODO: Max. size depends on chip, check that too if possible.
	258	if self.addr % 4096 != 0:
	259	# Sector addresses must be 4K-aligned (same for all 3 chips).
	260	d = 'Warning: Invalid sector address!'
	261	self.put(self.ss_block, self.es, self.out_ann, [101, [d]])
	262	self.state = None
	263	else:
	264	self.cmdstate += 1
	265
	266	def handle_be(self, mosi, miso):
	267	pass # TODO
	268
	269	def handle_ce(self, mosi, miso):
	270	pass # TODO
	271
	272	def handle_ce2(self, mosi, miso):
	273	pass # TODO
	274
	275	def handle_pp(self, mosi, miso):
	276	# Page program: Master asserts CS#, sends PP command, sends 3-byte
	277	# page address, sends >= 1 data bytes, de-asserts CS#.
	278	if self.cmdstate == 1:
	279	# Byte 1: Master sends command ID.
	280	self.putx([12, ['Command: %s' % cmds[self.state][1]]])
	281	elif self.cmdstate in (2, 3, 4):
	282	# Bytes 2/3/4: Master sends page address (24bits, MSB-first).
	283	self.addr \|= (mosi << ((4 - self.cmdstate) * 8))
	284	# self.putx([0, ['Page address, byte %d: 0x%02x' % \
	285	# (4 - self.cmdstate, mosi)]])
	286	if self.cmdstate == 4:
	287	self.putx([24, ['Page address: 0x%06x' % self.addr]])
	288	self.addr = 0
	289	elif self.cmdstate >= 5:
	290	# Bytes 5-x: Master sends data bytes (until CS# de-asserted).
	291	if self.cmdstate == 5:
	292	self.ss_block = self.ss
	293	self.on_end_transaction = lambda: self.output_data_block('Page data')
	294	self.data.append(mosi)
	295
	296	self.cmdstate += 1
	297
	298	def handle_cp(self, mosi, miso):
	299	pass # TODO
	300
	301	def handle_dp(self, mosi, miso):
	302	pass # TODO
	303
	304	def handle_rdp_res(self, mosi, miso):
	305	pass # TODO
	306
	307	def handle_rems(self, mosi, miso):
	308	if self.cmdstate == 1:
	309	# Byte 1: Master sends command ID.
	310	self.ss_block = self.ss
	311	self.putx([16, ['Command: %s' % cmds[self.state][1]]])
	312	elif self.cmdstate in (2, 3):
	313	# Bytes 2/3: Master sends two dummy bytes.
	314	# TODO: Check dummy bytes? Check reply from device?
	315	self.putx([24, ['Dummy byte: %s' % mosi]])
	316	elif self.cmdstate == 4:
	317	# Byte 4: Master sends 0x00 or 0x01.
	318	# 0x00: Master wants manufacturer ID as first reply byte.
	319	# 0x01: Master wants device ID as first reply byte.
	320	self.manufacturer_id_first = True if (mosi == 0x00) else False
	321	d = 'manufacturer' if (mosi == 0x00) else 'device'
	322	self.putx([24, ['Master wants %s ID first' % d]])
	323	elif self.cmdstate == 5:
	324	# Byte 5: Slave sends manufacturer ID (or device ID).
	325	self.ids = [miso]
	326	d = 'Manufacturer' if self.manufacturer_id_first else 'Device'
	327	self.putx([24, ['%s ID' % d]])
	328	elif self.cmdstate == 6:
	329	# Byte 6: Slave sends device ID (or manufacturer ID).
	330	self.ids.append(miso)
	331	d = 'Manufacturer' if self.manufacturer_id_first else 'Device'
	332	self.putx([24, ['%s ID' % d]])
	333
	334	if self.cmdstate == 6:
	335	id = self.ids[1] if self.manufacturer_id_first else self.ids[0]
	336	self.putx([24, ['Device: Macronix %s' % device_name[id]]])
	337	self.state = None
	338	else:
	339	self.cmdstate += 1
	340
	341	def handle_rems2(self, mosi, miso):
	342	pass # TODO
	343
	344	def handle_enso(self, mosi, miso):
	345	pass # TODO
	346
	347	def handle_exso(self, mosi, miso):
	348	pass # TODO
	349
	350	def handle_rdscur(self, mosi, miso):
	351	pass # TODO
	352
	353	def handle_wrscur(self, mosi, miso):
	354	pass # TODO
	355
	356	def handle_esry(self, mosi, miso):
	357	pass # TODO
	358
	359	def handle_dsry(self, mosi, miso):
	360	pass # TODO
	361
	362	def output_data_block(self, label):
	363	# Print accumulated block of data
	364	# (called on CS# de-assert via self.on_end_transaction callback).
	365	self.es_block = self.es # Ends on the CS# de-assert sample.
	366	if self.options['format'] == 'hex':
	367	s = ' '.join([('%02x' % b) for b in self.data])
	368	else:
	369	s = ''.join(map(chr, self.data))
	370	self.putb([25, ['%s %d bytes: %s' % (label, len(self.data), s)]])
	371
	372	def decode(self, ss, es, data):
	373	ptype, mosi, miso = data
	374
	375	self.ss, self.es = ss, es
	376
	377	if ptype == 'CS-CHANGE':
	378	self.end_current_transaction()
	379
	380	if ptype != 'DATA':
	381	return
	382
	383	# If we encountered a known chip command, enter the resp. state.
	384	if self.state is None:
	385	self.state = mosi
	386	self.cmdstate = 1
	387
	388	# Handle commands.
	389	try:
	390	self.cmd_handlers[self.state](mosi, miso)
	391	except KeyError:
	392	self.putx([24, ['Unknown command: 0x%02x' % mosi]])
	393	self.state = None