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1 | ## | |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2011-2015 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | import sigrokdecode as srd | |
22 | from .lists import * | |
23 | ||
24 | def cmd_annotation_classes(): | |
25 | return tuple([tuple([cmd[0].lower(), cmd[1]]) for cmd in cmds.values()]) | |
26 | ||
27 | def decode_dual_bytes(sio0, sio1): | |
28 | # Given a byte in SIO0 (MOSI) of even bits and a byte in | |
29 | # SIO1 (MISO) of odd bits, return a tuple of two bytes. | |
30 | def combine_byte(even, odd): | |
31 | result = 0 | |
32 | for bit in range(4): | |
33 | if even & (1 << bit): | |
34 | result |= 1 << (bit*2) | |
35 | if odd & (1 << bit): | |
36 | result |= 1 << ((bit*2) + 1) | |
37 | return result | |
38 | return (combine_byte(sio0 >> 4, sio1 >> 4), combine_byte(sio0, sio1)) | |
39 | ||
40 | def decode_status_reg(data): | |
41 | # TODO: Additional per-bit(s) self.put() calls with correct start/end. | |
42 | ||
43 | # Bits[0:0]: WIP (write in progress) | |
44 | s = 'W' if (data & (1 << 0)) else 'No w' | |
45 | ret = '%srite operation in progress.\n' % s | |
46 | ||
47 | # Bits[1:1]: WEL (write enable latch) | |
48 | s = '' if (data & (1 << 1)) else 'not ' | |
49 | ret += 'Internal write enable latch is %sset.\n' % s | |
50 | ||
51 | # Bits[5:2]: Block protect bits | |
52 | # TODO: More detailed decoding (chip-dependent). | |
53 | ret += 'Block protection bits (BP3-BP0): 0x%x.\n' % ((data & 0x3c) >> 2) | |
54 | ||
55 | # Bits[6:6]: Continuously program mode (CP mode) | |
56 | s = '' if (data & (1 << 6)) else 'not ' | |
57 | ret += 'Device is %sin continuously program mode (CP mode).\n' % s | |
58 | ||
59 | # Bits[7:7]: SRWD (status register write disable) | |
60 | s = 'not ' if (data & (1 << 7)) else '' | |
61 | ret += 'Status register writes are %sallowed.\n' % s | |
62 | ||
63 | return ret | |
64 | ||
65 | class Decoder(srd.Decoder): | |
66 | api_version = 2 | |
67 | id = 'spiflash' | |
68 | name = 'SPI flash' | |
69 | longname = 'SPI flash chips' | |
70 | desc = 'xx25 series SPI (NOR) flash chip protocol.' | |
71 | license = 'gplv2+' | |
72 | inputs = ['spi'] | |
73 | outputs = ['spiflash'] | |
74 | annotations = cmd_annotation_classes() + ( | |
75 | ('bits', 'Bits'), | |
76 | ('bits2', 'Bits2'), | |
77 | ('warnings', 'Warnings'), | |
78 | ) | |
79 | annotation_rows = ( | |
80 | ('bits', 'Bits', (24, 25)), | |
81 | ('commands', 'Commands', tuple(range(23 + 1))), | |
82 | ('warnings', 'Warnings', (26,)), | |
83 | ) | |
84 | options = ( | |
85 | {'id': 'chip', 'desc': 'Chip', 'default': tuple(chips.keys())[0], | |
86 | 'values': tuple(chips.keys())}, | |
87 | ) | |
88 | ||
89 | def __init__(self): | |
90 | self.on_end_transaction = None | |
91 | self.end_current_transaction() | |
92 | ||
93 | def end_current_transaction(self): | |
94 | if self.on_end_transaction is not None: # Callback for CS# transition. | |
95 | self.on_end_transaction() | |
96 | self.on_end_transaction = None | |
97 | self.state = None | |
98 | self.cmdstate = 1 | |
99 | self.addr = 0 | |
100 | self.data = [] | |
101 | ||
102 | def start(self): | |
103 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
104 | self.chip = chips[self.options['chip']] | |
105 | ||
106 | def putx(self, data): | |
107 | # Simplification, most annotations span exactly one SPI byte/packet. | |
108 | self.put(self.ss, self.es, self.out_ann, data) | |
109 | ||
110 | def putb(self, data): | |
111 | self.put(self.ss_block, self.es_block, self.out_ann, data) | |
112 | ||
113 | def handle_wren(self, mosi, miso): | |
114 | self.putx([0, ['Command: %s' % cmds[self.state][1]]]) | |
115 | self.state = None | |
116 | ||
117 | def handle_wrdi(self, mosi, miso): | |
118 | pass # TODO | |
119 | ||
120 | # TODO: Check/display device ID / name | |
121 | def handle_rdid(self, mosi, miso): | |
122 | if self.cmdstate == 1: | |
123 | # Byte 1: Master sends command ID. | |
124 | self.ss_block = self.ss | |
125 | self.putx([2, ['Command: %s' % cmds[self.state][1]]]) | |
126 | elif self.cmdstate == 2: | |
127 | # Byte 2: Slave sends the JEDEC manufacturer ID. | |
128 | self.putx([2, ['Manufacturer ID: 0x%02x' % miso]]) | |
129 | elif self.cmdstate == 3: | |
130 | # Byte 3: Slave sends the memory type (0x20 for this chip). | |
131 | self.putx([2, ['Memory type: 0x%02x' % miso]]) | |
132 | elif self.cmdstate == 4: | |
133 | # Byte 4: Slave sends the device ID. | |
134 | self.device_id = miso | |
135 | self.putx([2, ['Device ID: 0x%02x' % miso]]) | |
136 | ||
137 | if self.cmdstate == 4: | |
138 | # TODO: Check self.device_id is valid & exists in device_names. | |
139 | # TODO: Same device ID? Check! | |
140 | d = 'Device: Macronix %s' % device_name[self.device_id] | |
141 | self.put(self.ss_block, self.es, self.out_ann, [0, [d]]) | |
142 | self.state = None | |
143 | else: | |
144 | self.cmdstate += 1 | |
145 | ||
146 | def handle_rdsr(self, mosi, miso): | |
147 | # Read status register: Master asserts CS#, sends RDSR command, | |
148 | # reads status register byte. If CS# is kept asserted, the status | |
149 | # register can be read continuously / multiple times in a row. | |
150 | # When done, the master de-asserts CS# again. | |
151 | if self.cmdstate == 1: | |
152 | # Byte 1: Master sends command ID. | |
153 | self.putx([3, ['Command: %s' % cmds[self.state][1]]]) | |
154 | elif self.cmdstate >= 2: | |
155 | # Bytes 2-x: Slave sends status register as long as master clocks. | |
156 | self.putx([24, ['Status register: 0x%02x' % miso]]) | |
157 | self.putx([25, [decode_status_reg(miso)]]) | |
158 | ||
159 | self.cmdstate += 1 | |
160 | ||
161 | def handle_wrsr(self, mosi, miso): | |
162 | pass # TODO | |
163 | ||
164 | def handle_read(self, mosi, miso): | |
165 | # Read data bytes: Master asserts CS#, sends READ command, sends | |
166 | # 3-byte address, reads >= 1 data bytes, de-asserts CS#. | |
167 | if self.cmdstate == 1: | |
168 | # Byte 1: Master sends command ID. | |
169 | self.putx([5, ['Command: %s' % cmds[self.state][1]]]) | |
170 | elif self.cmdstate in (2, 3, 4): | |
171 | # Bytes 2/3/4: Master sends read address (24bits, MSB-first). | |
172 | self.addr |= (mosi << ((4 - self.cmdstate) * 8)) | |
173 | # self.putx([0, ['Read address, byte %d: 0x%02x' % \ | |
174 | # (4 - self.cmdstate, mosi)]]) | |
175 | if self.cmdstate == 4: | |
176 | self.putx([24, ['Read address: 0x%06x' % self.addr]]) | |
177 | self.addr = 0 | |
178 | elif self.cmdstate >= 5: | |
179 | # Bytes 5-x: Master reads data bytes (until CS# de-asserted). | |
180 | if self.cmdstate == 5: | |
181 | self.ss_block = self.ss | |
182 | self.on_end_transaction = lambda: self.output_data_block('Read') | |
183 | self.data.append(miso) | |
184 | ||
185 | self.cmdstate += 1 | |
186 | ||
187 | def handle_fast_read(self, mosi, miso): | |
188 | # Fast read: Master asserts CS#, sends FAST READ command, sends | |
189 | # 3-byte address + 1 dummy byte, reads >= 1 data bytes, de-asserts CS#. | |
190 | if self.cmdstate == 1: | |
191 | # Byte 1: Master sends command ID. | |
192 | self.putx([5, ['Command: %s' % cmds[self.state][1]]]) | |
193 | elif self.cmdstate in (2, 3, 4): | |
194 | # Bytes 2/3/4: Master sends read address (24bits, MSB-first). | |
195 | self.putx([24, ['AD%d: 0x%02x' % (self.cmdstate - 1, mosi)]]) | |
196 | if self.cmdstate == 2: | |
197 | self.ss_block = self.ss | |
198 | self.addr |= (mosi << ((4 - self.cmdstate) * 8)) | |
199 | elif self.cmdstate == 5: | |
200 | self.putx([24, ['Dummy byte: 0x%02x' % mosi]]) | |
201 | self.es_block = self.es | |
202 | self.putb([5, ['Read address: 0x%06x' % self.addr]]) | |
203 | self.addr = 0 | |
204 | elif self.cmdstate >= 6: | |
205 | # Bytes 6-x: Master reads data bytes (until CS# de-asserted). | |
206 | if self.cmdstate == 6: | |
207 | self.ss_block = self.ss | |
208 | self.on_end_transaction = lambda: self.output_data_block('Read') | |
209 | self.data.append(miso) | |
210 | ||
211 | self.cmdstate += 1 | |
212 | ||
213 | def handle_2read(self, mosi, miso): | |
214 | # Fast read dual I/O: Same as fast read, but all data | |
215 | # after the command is sent via two I/O pins. | |
216 | # MOSI = SIO0 = even bits, MISO = SIO1 = odd bits. | |
217 | # Recombine the bytes and pass them up to the handle_fast_read command. | |
218 | if self.cmdstate == 1: | |
219 | # Byte 1: Master sends command ID. | |
220 | self.putx([5, ['Command: %s' % cmds[self.state][1]]]) | |
221 | self.cmdstate = 2 | |
222 | else: | |
223 | # Dual I/O mode. | |
224 | a, b = decode_dual_bytes(mosi, miso) | |
225 | # Pass same byte in as both MISO & MOSI, parser state determines | |
226 | # which one it cares about. | |
227 | self.handle_fast_read(a, a) | |
228 | self.handle_fast_read(b, b) | |
229 | ||
230 | # TODO: Warn/abort if we don't see the necessary amount of bytes. | |
231 | # TODO: Warn if WREN was not seen before. | |
232 | def handle_se(self, mosi, miso): | |
233 | if self.cmdstate == 1: | |
234 | # Byte 1: Master sends command ID. | |
235 | self.addr = 0 | |
236 | self.ss_block = self.ss | |
237 | self.putx([8, ['Command: %s' % cmds[self.state][1]]]) | |
238 | elif self.cmdstate in (2, 3, 4): | |
239 | # Bytes 2/3/4: Master sends sector address (24bits, MSB-first). | |
240 | self.addr |= (mosi << ((4 - self.cmdstate) * 8)) | |
241 | # self.putx([0, ['Sector address, byte %d: 0x%02x' % \ | |
242 | # (4 - self.cmdstate, mosi)]]) | |
243 | ||
244 | if self.cmdstate == 4: | |
245 | d = 'Erase sector %d (0x%06x)' % (self.addr, self.addr) | |
246 | self.put(self.ss_block, self.es, self.out_ann, [24, [d]]) | |
247 | # TODO: Max. size depends on chip, check that too if possible. | |
248 | if self.addr % 4096 != 0: | |
249 | # Sector addresses must be 4K-aligned (same for all 3 chips). | |
250 | d = 'Warning: Invalid sector address!' | |
251 | self.put(self.ss_block, self.es, self.out_ann, [101, [d]]) | |
252 | self.state = None | |
253 | else: | |
254 | self.cmdstate += 1 | |
255 | ||
256 | def handle_be(self, mosi, miso): | |
257 | pass # TODO | |
258 | ||
259 | def handle_ce(self, mosi, miso): | |
260 | pass # TODO | |
261 | ||
262 | def handle_ce2(self, mosi, miso): | |
263 | pass # TODO | |
264 | ||
265 | def handle_pp(self, mosi, miso): | |
266 | # Page program: Master asserts CS#, sends PP command, sends 3-byte | |
267 | # page address, sends >= 1 data bytes, de-asserts CS#. | |
268 | if self.cmdstate == 1: | |
269 | # Byte 1: Master sends command ID. | |
270 | self.putx([12, ['Command: %s' % cmds[self.state][1]]]) | |
271 | elif self.cmdstate in (2, 3, 4): | |
272 | # Bytes 2/3/4: Master sends page address (24bits, MSB-first). | |
273 | self.addr |= (mosi << ((4 - self.cmdstate) * 8)) | |
274 | # self.putx([0, ['Page address, byte %d: 0x%02x' % \ | |
275 | # (4 - self.cmdstate, mosi)]]) | |
276 | if self.cmdstate == 4: | |
277 | self.putx([24, ['Page address: 0x%06x' % self.addr]]) | |
278 | self.addr = 0 | |
279 | elif self.cmdstate >= 5: | |
280 | # Bytes 5-x: Master sends data bytes (until CS# de-asserted). | |
281 | if self.cmdstate == 5: | |
282 | self.ss_block = self.ss | |
283 | self.on_end_transaction = lambda: self.output_data_block('Page data') | |
284 | self.data.append(mosi) | |
285 | ||
286 | self.cmdstate += 1 | |
287 | ||
288 | def handle_cp(self, mosi, miso): | |
289 | pass # TODO | |
290 | ||
291 | def handle_dp(self, mosi, miso): | |
292 | pass # TODO | |
293 | ||
294 | def handle_rdp_res(self, mosi, miso): | |
295 | pass # TODO | |
296 | ||
297 | def handle_rems(self, mosi, miso): | |
298 | if self.cmdstate == 1: | |
299 | # Byte 1: Master sends command ID. | |
300 | self.ss_block = self.ss | |
301 | self.putx([16, ['Command: %s' % cmds[self.state][1]]]) | |
302 | elif self.cmdstate in (2, 3): | |
303 | # Bytes 2/3: Master sends two dummy bytes. | |
304 | # TODO: Check dummy bytes? Check reply from device? | |
305 | self.putx([24, ['Dummy byte: %s' % mosi]]) | |
306 | elif self.cmdstate == 4: | |
307 | # Byte 4: Master sends 0x00 or 0x01. | |
308 | # 0x00: Master wants manufacturer ID as first reply byte. | |
309 | # 0x01: Master wants device ID as first reply byte. | |
310 | self.manufacturer_id_first = True if (mosi == 0x00) else False | |
311 | d = 'manufacturer' if (mosi == 0x00) else 'device' | |
312 | self.putx([24, ['Master wants %s ID first' % d]]) | |
313 | elif self.cmdstate == 5: | |
314 | # Byte 5: Slave sends manufacturer ID (or device ID). | |
315 | self.ids = [miso] | |
316 | d = 'Manufacturer' if self.manufacturer_id_first else 'Device' | |
317 | self.putx([24, ['%s ID' % d]]) | |
318 | elif self.cmdstate == 6: | |
319 | # Byte 6: Slave sends device ID (or manufacturer ID). | |
320 | self.ids.append(miso) | |
321 | d = 'Manufacturer' if self.manufacturer_id_first else 'Device' | |
322 | self.putx([24, ['%s ID' % d]]) | |
323 | ||
324 | if self.cmdstate == 6: | |
325 | id = self.ids[1] if self.manufacturer_id_first else self.ids[0] | |
326 | self.putx([24, ['Device: Macronix %s' % device_name[id]]]) | |
327 | self.state = None | |
328 | else: | |
329 | self.cmdstate += 1 | |
330 | ||
331 | def handle_rems2(self, mosi, miso): | |
332 | pass # TODO | |
333 | ||
334 | def handle_enso(self, mosi, miso): | |
335 | pass # TODO | |
336 | ||
337 | def handle_exso(self, mosi, miso): | |
338 | pass # TODO | |
339 | ||
340 | def handle_rdscur(self, mosi, miso): | |
341 | pass # TODO | |
342 | ||
343 | def handle_wrscur(self, mosi, miso): | |
344 | pass # TODO | |
345 | ||
346 | def handle_esry(self, mosi, miso): | |
347 | pass # TODO | |
348 | ||
349 | def handle_dsry(self, mosi, miso): | |
350 | pass # TODO | |
351 | ||
352 | def output_data_block(self, label): | |
353 | # Print accumulated block of data | |
354 | # (called on CS# de-assert via self.on_end_transaction callback). | |
355 | self.es_block = self.es # Ends on the CS# de-assert sample. | |
356 | s = ' '.join([('%02x' % b) for b in self.data]) | |
357 | self.putb([25, ['%s %d bytes: %s' % (label, len(self.data), s)]]) | |
358 | ||
359 | def decode(self, ss, es, data): | |
360 | ptype, mosi, miso = data | |
361 | ||
362 | self.ss, self.es = ss, es | |
363 | ||
364 | if ptype == 'CS-CHANGE': | |
365 | self.end_current_transaction() | |
366 | ||
367 | if ptype != 'DATA': | |
368 | return | |
369 | ||
370 | # If we encountered a known chip command, enter the resp. state. | |
371 | if self.state is None: | |
372 | self.state = mosi | |
373 | self.cmdstate = 1 | |
374 | ||
375 | # Handle commands. | |
376 | if self.state in cmds: | |
377 | s = 'handle_%s' % cmds[self.state][0].lower().replace('/', '_') | |
378 | handle_reg = getattr(self, s) | |
379 | handle_reg(mosi, miso) | |
380 | else: | |
381 | self.putx([24, ['Unknown command: 0x%02x' % mosi]]) | |
382 | self.state = None |