]>
Commit | Line | Data |
---|---|---|
1 | ## | |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz> | |
5 | ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de> | |
6 | ## | |
7 | ## This program is free software; you can redistribute it and/or modify | |
8 | ## it under the terms of the GNU General Public License as published by | |
9 | ## the Free Software Foundation; either version 2 of the License, or | |
10 | ## (at your option) any later version. | |
11 | ## | |
12 | ## This program is distributed in the hope that it will be useful, | |
13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ## GNU General Public License for more details. | |
16 | ## | |
17 | ## You should have received a copy of the GNU General Public License | |
18 | ## along with this program; if not, write to the Free Software | |
19 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | ## | |
21 | ||
22 | # SPI protocol decoder | |
23 | ||
24 | import sigrokdecode as srd | |
25 | ||
26 | # Key: (CPOL, CPHA). Value: SPI mode. | |
27 | # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive. | |
28 | # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge. | |
29 | spi_mode = { | |
30 | (0, 0): 0, # Mode 0 | |
31 | (0, 1): 1, # Mode 1 | |
32 | (1, 0): 2, # Mode 2 | |
33 | (1, 1): 3, # Mode 3 | |
34 | } | |
35 | ||
36 | class Decoder(srd.Decoder): | |
37 | api_version = 1 | |
38 | id = 'spi' | |
39 | name = 'SPI' | |
40 | longname = 'Serial Peripheral Interface' | |
41 | desc = 'Full-duplex, synchronous, serial bus.' | |
42 | license = 'gplv2+' | |
43 | inputs = ['logic'] | |
44 | outputs = ['spi'] | |
45 | probes = [ | |
46 | {'id': 'miso', 'name': 'MISO', | |
47 | 'desc': 'SPI MISO line (Master in, slave out)'}, | |
48 | {'id': 'mosi', 'name': 'MOSI', | |
49 | 'desc': 'SPI MOSI line (Master out, slave in)'}, | |
50 | {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'}, | |
51 | {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'}, | |
52 | ] | |
53 | optional_probes = [] # TODO | |
54 | options = { | |
55 | 'cs_polarity': ['CS# polarity', 'active-low'], | |
56 | 'cpol': ['Clock polarity', 0], | |
57 | 'cpha': ['Clock phase', 0], | |
58 | 'bitorder': ['Bit order within the SPI data', 'msb-first'], | |
59 | 'wordsize': ['Word size of SPI data', 8], # 1-64? | |
60 | 'format': ['Data format', 'hex'], | |
61 | } | |
62 | annotations = [ | |
63 | ['Data', 'SPI data'], | |
64 | ['Warnings', 'Human-readable warnings'], | |
65 | ] | |
66 | ||
67 | def __init__(self): | |
68 | self.oldsck = 1 | |
69 | self.bitcount = 0 | |
70 | self.mosidata = 0 | |
71 | self.misodata = 0 | |
72 | self.bytesreceived = 0 | |
73 | self.startsample = -1 | |
74 | self.samplenum = -1 | |
75 | self.cs_was_deasserted_during_data_word = 0 | |
76 | self.oldcs = -1 | |
77 | self.oldpins = None | |
78 | ||
79 | def start(self, metadata): | |
80 | self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi') | |
81 | self.out_ann = self.add(srd.OUTPUT_ANN, 'spi') | |
82 | ||
83 | def report(self): | |
84 | return 'SPI: %d bytes received' % self.bytesreceived | |
85 | ||
86 | def putpw(self, data): | |
87 | self.put(self.startsample, self.samplenum, self.out_proto, data) | |
88 | ||
89 | def putw(self, data): | |
90 | self.put(self.startsample, self.samplenum, self.out_ann, data) | |
91 | ||
92 | def decode(self, ss, es, data): | |
93 | # TODO: Either MISO or MOSI could be optional. CS# is optional. | |
94 | for (self.samplenum, pins) in data: | |
95 | ||
96 | # Ignore identical samples early on (for performance reasons). | |
97 | if self.oldpins == pins: | |
98 | continue | |
99 | self.oldpins, (miso, mosi, sck, cs) = pins, pins | |
100 | ||
101 | if self.oldcs != cs: | |
102 | # Send all CS# pin value changes. | |
103 | self.put(self.samplenum, self.samplenum, self.out_proto, | |
104 | ['CS-CHANGE', self.oldcs, cs]) | |
105 | self.oldcs = cs | |
106 | ||
107 | # Ignore sample if the clock pin hasn't changed. | |
108 | if sck == self.oldsck: | |
109 | continue | |
110 | ||
111 | self.oldsck = sck | |
112 | ||
113 | # Sample data on rising/falling clock edge (depends on mode). | |
114 | mode = spi_mode[self.options['cpol'], self.options['cpha']] | |
115 | if mode == 0 and sck == 0: # Sample on rising clock edge | |
116 | continue | |
117 | elif mode == 1 and sck == 1: # Sample on falling clock edge | |
118 | continue | |
119 | elif mode == 2 and sck == 1: # Sample on falling clock edge | |
120 | continue | |
121 | elif mode == 3 and sck == 0: # Sample on rising clock edge | |
122 | continue | |
123 | ||
124 | # If this is the first bit, save its sample number. | |
125 | if self.bitcount == 0: | |
126 | self.startsample = self.samplenum | |
127 | active_low = (self.options['cs_polarity'] == 'active-low') | |
128 | deasserted = cs if active_low else not cs | |
129 | if deasserted: | |
130 | self.cs_was_deasserted_during_data_word = 1 | |
131 | ||
132 | ws = self.options['wordsize'] | |
133 | ||
134 | # Receive MOSI bit into our shift register. | |
135 | if self.options['bitorder'] == 'msb-first': | |
136 | self.mosidata |= mosi << (ws - 1 - self.bitcount) | |
137 | else: | |
138 | self.mosidata |= mosi << self.bitcount | |
139 | ||
140 | # Receive MISO bit into our shift register. | |
141 | if self.options['bitorder'] == 'msb-first': | |
142 | self.misodata |= miso << (ws - 1 - self.bitcount) | |
143 | else: | |
144 | self.misodata |= miso << self.bitcount | |
145 | ||
146 | self.bitcount += 1 | |
147 | ||
148 | # Continue to receive if not enough bits were received, yet. | |
149 | if self.bitcount != ws: | |
150 | continue | |
151 | ||
152 | self.putpw(['DATA', self.mosidata, self.misodata]) | |
153 | self.putw([0, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata, | |
154 | self.misodata)]]) | |
155 | ||
156 | if self.cs_was_deasserted_during_data_word: | |
157 | self.putw([1, ['CS# was deasserted during this data word!']]) | |
158 | ||
159 | # Reset decoder state. | |
160 | self.mosidata = 0 | |
161 | self.misodata = 0 | |
162 | self.bitcount = 0 | |
163 | ||
164 | # Keep stats for summary. | |
165 | self.bytesreceived += 1 | |
166 |