[libsigrokdecode.git] / decoders / spi / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

# SPI protocol decoder

import sigrokdecode as srd

'''
Protocol output format:

SPI packet:
[<cmd>, <data1>, <data2>]

Commands:
 - 'DATA': <data1> contains the MISO data, <data2> contains the MOSI data.
   The data is _usually_ 8 bits (but can also be fewer or more bits).
   Both data items are Python numbers, not strings.
 - 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
   Both data items are Python numbers (0/1), not strings.

Examples:
 ['CS-CHANGE', 1, 0]
 ['DATA', 0xff, 0x3a]
 ['DATA', 0x65, 0x00]
 ['CS-CHANGE', 0, 1]
'''

# Key: (CPOL, CPHA). Value: SPI mode.
# Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
# Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
spi_mode = {
    (0, 0): 0, # Mode 0
    (0, 1): 1, # Mode 1
    (1, 0): 2, # Mode 2
    (1, 1): 3, # Mode 3
}

class Decoder(srd.Decoder):
    api_version = 1
    id = 'spi'
    name = 'SPI'
    longname = 'Serial Peripheral Interface'
    desc = 'Full-duplex, synchronous, serial bus.'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['spi']
    probes = [
        {'id': 'miso', 'name': 'MISO',
         'desc': 'SPI MISO line (Master in, slave out)'},
        {'id': 'mosi', 'name': 'MOSI',
         'desc': 'SPI MOSI line (Master out, slave in)'},
        {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
    ]
    optional_probes = [
        {'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'},
    ]
    options = {
        'cs_polarity': ['CS# polarity', 'active-low'],
        'cpol': ['Clock polarity', 0],
        'cpha': ['Clock phase', 0],
        'bitorder': ['Bit order within the SPI data', 'msb-first'],
        'wordsize': ['Word size of SPI data', 8], # 1-64?
        'format': ['Data format', 'hex'],
    }
    annotations = [
        ['MISO/MOSI data', 'MISO/MOSI SPI data'],
        ['MISO data', 'MISO SPI data'],
        ['MOSI data', 'MOSI SPI data'],
        ['Warnings', 'Human-readable warnings'],
    ]

    def __init__(self):
        self.oldsck = 1
        self.bitcount = 0
        self.mosidata = 0
        self.misodata = 0
        self.bytesreceived = 0
        self.startsample = -1
        self.samplenum = -1
        self.cs_was_deasserted_during_data_word = 0
        self.oldcs = -1
        self.oldpins = None
        self.state = 'IDLE'

    def start(self):
        self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
        self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')

    def report(self):
        return 'SPI: %d bytes received' % self.bytesreceived

    def putpw(self, data):
        self.put(self.startsample, self.samplenum, self.out_proto, data)

    def putw(self, data):
        self.put(self.startsample, self.samplenum, self.out_ann, data)

    def handle_bit(self, miso, mosi, sck, cs):
        # If this is the first bit, save its sample number.
        if self.bitcount == 0:
            self.startsample = self.samplenum
            if self.have_cs:
                active_low = (self.options['cs_polarity'] == 'active-low')
                deasserted = cs if active_low else not cs
                if deasserted:
                    self.cs_was_deasserted_during_data_word = 1

        ws = self.options['wordsize']

        # Receive MOSI bit into our shift register.
        if self.options['bitorder'] == 'msb-first':
            self.mosidata |= mosi << (ws - 1 - self.bitcount)
        else:
            self.mosidata |= mosi << self.bitcount

        # Receive MISO bit into our shift register.
        if self.options['bitorder'] == 'msb-first':
            self.misodata |= miso << (ws - 1 - self.bitcount)
        else:
            self.misodata |= miso << self.bitcount

        self.bitcount += 1

        # Continue to receive if not enough bits were received, yet.
        if self.bitcount != ws:
            return

        self.putpw(['DATA', self.mosidata, self.misodata])
        self.putw([0, ['%02X/%02X' % (self.mosidata, self.misodata)]])
        self.putw([1, ['%02X' % self.misodata]])
        self.putw([2, ['%02X' % self.mosidata]])

        if self.cs_was_deasserted_during_data_word:
            self.putw([3, ['CS# was deasserted during this data word!']])

        # Reset decoder state.
        self.mosidata = self.misodata = self.bitcount = 0

        # Keep stats for summary.
        self.bytesreceived += 1

    def find_clk_edge(self, miso, mosi, sck, cs):
        if self.have_cs and self.oldcs != cs:
            # Send all CS# pin value changes.
            self.put(self.samplenum, self.samplenum, self.out_proto,
                     ['CS-CHANGE', self.oldcs, cs])
            self.oldcs = cs
            # Reset decoder state when CS# changes (and the CS# pin is used).
            self.mosidata = self.misodata = self.bitcount= 0

        # Ignore sample if the clock pin hasn't changed.
        if sck == self.oldsck:
            return

        self.oldsck = sck

        # Sample data on rising/falling clock edge (depends on mode).
        mode = spi_mode[self.options['cpol'], self.options['cpha']]
        if mode == 0 and sck == 0:   # Sample on rising clock edge
            return
        elif mode == 1 and sck == 1: # Sample on falling clock edge
            return
        elif mode == 2 and sck == 1: # Sample on falling clock edge
            return
        elif mode == 3 and sck == 0: # Sample on rising clock edge
            return

        # Found the correct clock edge, now get the SPI bit(s).
        self.handle_bit(miso, mosi, sck, cs)

    def decode(self, ss, es, data):
        # TODO: Either MISO or MOSI could be optional. CS# is optional.
        for (self.samplenum, pins) in data:

            # Ignore identical samples early on (for performance reasons).
            if self.oldpins == pins:
                continue
            self.oldpins, (miso, mosi, sck, cs) = pins, pins
            self.have_cs = (cs in (0, 1))

            # State machine.
            if self.state == 'IDLE':
                self.find_clk_edge(miso, mosi, sck, cs)
            else:
                raise Exception('Invalid state: %s' % self.state)
Commit	Line	Data
	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
	5	## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
	6	##
	7	## This program is free software; you can redistribute it and/or modify
	8	## it under the terms of the GNU General Public License as published by
	9	## the Free Software Foundation; either version 2 of the License, or
	10	## (at your option) any later version.
	11	##
	12	## This program is distributed in the hope that it will be useful,
	13	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	## GNU General Public License for more details.
	16	##
	17	## You should have received a copy of the GNU General Public License
	18	## along with this program; if not, write to the Free Software
	19	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	20	##
	21
	22	# SPI protocol decoder
	23
	24	import sigrokdecode as srd
	25
	26	'''
	27	Protocol output format:
	28
	29	SPI packet:
	30	[<cmd>, <data1>, <data2>]
	31
	32	Commands:
	33	- 'DATA': <data1> contains the MISO data, <data2> contains the MOSI data.
	34	The data is _usually_ 8 bits (but can also be fewer or more bits).
	35	Both data items are Python numbers, not strings.
	36	- 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
	37	Both data items are Python numbers (0/1), not strings.
	38
	39	Examples:
	40	['CS-CHANGE', 1, 0]
	41	['DATA', 0xff, 0x3a]
	42	['DATA', 0x65, 0x00]
	43	['CS-CHANGE', 0, 1]
	44	'''
	45
	46	# Key: (CPOL, CPHA). Value: SPI mode.
	47	# Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
	48	# Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
	49	spi_mode = {
	50	(0, 0): 0, # Mode 0
	51	(0, 1): 1, # Mode 1
	52	(1, 0): 2, # Mode 2
	53	(1, 1): 3, # Mode 3
	54	}
	55
	56	class Decoder(srd.Decoder):
	57	api_version = 1
	58	id = 'spi'
	59	name = 'SPI'
	60	longname = 'Serial Peripheral Interface'
	61	desc = 'Full-duplex, synchronous, serial bus.'
	62	license = 'gplv2+'
	63	inputs = ['logic']
	64	outputs = ['spi']
	65	probes = [
	66	{'id': 'miso', 'name': 'MISO',
	67	'desc': 'SPI MISO line (Master in, slave out)'},
	68	{'id': 'mosi', 'name': 'MOSI',
	69	'desc': 'SPI MOSI line (Master out, slave in)'},
	70	{'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
	71	]
	72	optional_probes = [
	73	{'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'},
	74	]
	75	options = {
	76	'cs_polarity': ['CS# polarity', 'active-low'],
	77	'cpol': ['Clock polarity', 0],
	78	'cpha': ['Clock phase', 0],
	79	'bitorder': ['Bit order within the SPI data', 'msb-first'],
	80	'wordsize': ['Word size of SPI data', 8], # 1-64?
	81	'format': ['Data format', 'hex'],
	82	}
	83	annotations = [
	84	['MISO/MOSI data', 'MISO/MOSI SPI data'],
	85	['MISO data', 'MISO SPI data'],
	86	['MOSI data', 'MOSI SPI data'],
	87	['Warnings', 'Human-readable warnings'],
	88	]
	89
	90	def __init__(self):
	91	self.oldsck = 1
	92	self.bitcount = 0
	93	self.mosidata = 0
	94	self.misodata = 0
	95	self.bytesreceived = 0
	96	self.startsample = -1
	97	self.samplenum = -1
	98	self.cs_was_deasserted_during_data_word = 0
	99	self.oldcs = -1
	100	self.oldpins = None
	101	self.state = 'IDLE'
	102
	103	def start(self):
	104	self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
	105	self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
	106
	107	def report(self):
	108	return 'SPI: %d bytes received' % self.bytesreceived
	109
	110	def putpw(self, data):
	111	self.put(self.startsample, self.samplenum, self.out_proto, data)
	112
	113	def putw(self, data):
	114	self.put(self.startsample, self.samplenum, self.out_ann, data)
	115
	116	def handle_bit(self, miso, mosi, sck, cs):
	117	# If this is the first bit, save its sample number.
	118	if self.bitcount == 0:
	119	self.startsample = self.samplenum
	120	if self.have_cs:
	121	active_low = (self.options['cs_polarity'] == 'active-low')
	122	deasserted = cs if active_low else not cs
	123	if deasserted:
	124	self.cs_was_deasserted_during_data_word = 1
	125
	126	ws = self.options['wordsize']
	127
	128	# Receive MOSI bit into our shift register.
	129	if self.options['bitorder'] == 'msb-first':
	130	self.mosidata \|= mosi << (ws - 1 - self.bitcount)
	131	else:
	132	self.mosidata \|= mosi << self.bitcount
	133
	134	# Receive MISO bit into our shift register.
	135	if self.options['bitorder'] == 'msb-first':
	136	self.misodata \|= miso << (ws - 1 - self.bitcount)
	137	else:
	138	self.misodata \|= miso << self.bitcount
	139
	140	self.bitcount += 1
	141
	142	# Continue to receive if not enough bits were received, yet.
	143	if self.bitcount != ws:
	144	return
	145
	146	self.putpw(['DATA', self.mosidata, self.misodata])
	147	self.putw([0, ['%02X/%02X' % (self.mosidata, self.misodata)]])
	148	self.putw([1, ['%02X' % self.misodata]])
	149	self.putw([2, ['%02X' % self.mosidata]])
	150
	151	if self.cs_was_deasserted_during_data_word:
	152	self.putw([3, ['CS# was deasserted during this data word!']])
	153
	154	# Reset decoder state.
	155	self.mosidata = self.misodata = self.bitcount = 0
	156
	157	# Keep stats for summary.
	158	self.bytesreceived += 1
	159
	160	def find_clk_edge(self, miso, mosi, sck, cs):
	161	if self.have_cs and self.oldcs != cs:
	162	# Send all CS# pin value changes.
	163	self.put(self.samplenum, self.samplenum, self.out_proto,
	164	['CS-CHANGE', self.oldcs, cs])
	165	self.oldcs = cs
	166	# Reset decoder state when CS# changes (and the CS# pin is used).
	167	self.mosidata = self.misodata = self.bitcount= 0
	168
	169	# Ignore sample if the clock pin hasn't changed.
	170	if sck == self.oldsck:
	171	return
	172
	173	self.oldsck = sck
	174
	175	# Sample data on rising/falling clock edge (depends on mode).
	176	mode = spi_mode[self.options['cpol'], self.options['cpha']]
	177	if mode == 0 and sck == 0: # Sample on rising clock edge
	178	return
	179	elif mode == 1 and sck == 1: # Sample on falling clock edge
	180	return
	181	elif mode == 2 and sck == 1: # Sample on falling clock edge
	182	return
	183	elif mode == 3 and sck == 0: # Sample on rising clock edge
	184	return
	185
	186	# Found the correct clock edge, now get the SPI bit(s).
	187	self.handle_bit(miso, mosi, sck, cs)
	188
	189	def decode(self, ss, es, data):
	190	# TODO: Either MISO or MOSI could be optional. CS# is optional.
	191	for (self.samplenum, pins) in data:
	192
	193	# Ignore identical samples early on (for performance reasons).
	194	if self.oldpins == pins:
	195	continue
	196	self.oldpins, (miso, mosi, sck, cs) = pins, pins
	197	self.have_cs = (cs in (0, 1))
	198
	199	# State machine.
	200	if self.state == 'IDLE':
	201	self.find_clk_edge(miso, mosi, sck, cs)
	202	else:
	203	raise Exception('Invalid state: %s' % self.state)
	204