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1 | ## | |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz> | |
5 | ## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de> | |
6 | ## | |
7 | ## This program is free software; you can redistribute it and/or modify | |
8 | ## it under the terms of the GNU General Public License as published by | |
9 | ## the Free Software Foundation; either version 2 of the License, or | |
10 | ## (at your option) any later version. | |
11 | ## | |
12 | ## This program is distributed in the hope that it will be useful, | |
13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ## GNU General Public License for more details. | |
16 | ## | |
17 | ## You should have received a copy of the GNU General Public License | |
18 | ## along with this program; if not, write to the Free Software | |
19 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | ## | |
21 | ||
22 | import sigrokdecode as srd | |
23 | from collections import namedtuple | |
24 | ||
25 | Data = namedtuple('Data', ['ss', 'es', 'val']) | |
26 | ||
27 | ''' | |
28 | OUTPUT_PYTHON format: | |
29 | ||
30 | Packet: | |
31 | [<ptype>, <data1>, <data2>] | |
32 | ||
33 | <ptype>: | |
34 | - 'DATA': <data1> contains the MOSI data, <data2> contains the MISO data. | |
35 | The data is _usually_ 8 bits (but can also be fewer or more bits). | |
36 | Both data items are Python numbers (not strings), or None if the respective | |
37 | channel was not supplied. | |
38 | - 'BITS': <data1>/<data2> contain a list of bit values in this MOSI/MISO data | |
39 | item, and for each of those also their respective start-/endsample numbers. | |
40 | - 'CS-CHANGE': <data1> is the old CS# pin value, <data2> is the new value. | |
41 | Both data items are Python numbers (0/1), not strings. At the beginning of | |
42 | the decoding a packet is generated with <data1> = None and <data2> being the | |
43 | initial state of the CS# pin or None if the chip select pin is not supplied. | |
44 | - 'TRANSFER': <data1>/<data2> contain a list of Data() namedtuples for each | |
45 | byte transferred during this block of CS# asserted time. Each Data() has | |
46 | fields ss, es, and val. | |
47 | ||
48 | Examples: | |
49 | ['CS-CHANGE', None, 1] | |
50 | ['CS-CHANGE', 1, 0] | |
51 | ['DATA', 0xff, 0x3a] | |
52 | ['BITS', [[1, 80, 82], [1, 83, 84], [1, 85, 86], [1, 87, 88], | |
53 | [1, 89, 90], [1, 91, 92], [1, 93, 94], [1, 95, 96]], | |
54 | [[0, 80, 82], [1, 83, 84], [0, 85, 86], [1, 87, 88], | |
55 | [1, 89, 90], [1, 91, 92], [0, 93, 94], [0, 95, 96]]] | |
56 | ['DATA', 0x65, 0x00] | |
57 | ['DATA', 0xa8, None] | |
58 | ['DATA', None, 0x55] | |
59 | ['CS-CHANGE', 0, 1] | |
60 | ['TRANSFER', [Data(ss=80, es=96, val=0xff), ...], | |
61 | [Data(ss=80, es=96, val=0x3a), ...]] | |
62 | ''' | |
63 | ||
64 | # Key: (CPOL, CPHA). Value: SPI mode. | |
65 | # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive. | |
66 | # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge. | |
67 | spi_mode = { | |
68 | (0, 0): 0, # Mode 0 | |
69 | (0, 1): 1, # Mode 1 | |
70 | (1, 0): 2, # Mode 2 | |
71 | (1, 1): 3, # Mode 3 | |
72 | } | |
73 | ||
74 | class SamplerateError(Exception): | |
75 | pass | |
76 | ||
77 | class ChannelError(Exception): | |
78 | pass | |
79 | ||
80 | class Decoder(srd.Decoder): | |
81 | api_version = 2 | |
82 | id = 'spi' | |
83 | name = 'SPI' | |
84 | longname = 'Serial Peripheral Interface' | |
85 | desc = 'Full-duplex, synchronous, serial bus.' | |
86 | license = 'gplv2+' | |
87 | inputs = ['logic'] | |
88 | outputs = ['spi'] | |
89 | channels = ( | |
90 | {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'}, | |
91 | ) | |
92 | optional_channels = ( | |
93 | {'id': 'miso', 'name': 'MISO', 'desc': 'Master in, slave out'}, | |
94 | {'id': 'mosi', 'name': 'MOSI', 'desc': 'Master out, slave in'}, | |
95 | {'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'}, | |
96 | ) | |
97 | options = ( | |
98 | {'id': 'cs_polarity', 'desc': 'CS# polarity', 'default': 'active-low', | |
99 | 'values': ('active-low', 'active-high')}, | |
100 | {'id': 'cpol', 'desc': 'Clock polarity', 'default': 0, | |
101 | 'values': (0, 1)}, | |
102 | {'id': 'cpha', 'desc': 'Clock phase', 'default': 0, | |
103 | 'values': (0, 1)}, | |
104 | {'id': 'bitorder', 'desc': 'Bit order', | |
105 | 'default': 'msb-first', 'values': ('msb-first', 'lsb-first')}, | |
106 | {'id': 'wordsize', 'desc': 'Word size', 'default': 8}, | |
107 | ) | |
108 | annotations = ( | |
109 | ('miso-data', 'MISO data'), | |
110 | ('mosi-data', 'MOSI data'), | |
111 | ('miso-bits', 'MISO bits'), | |
112 | ('mosi-bits', 'MOSI bits'), | |
113 | ('warnings', 'Human-readable warnings'), | |
114 | ) | |
115 | annotation_rows = ( | |
116 | ('miso-data', 'MISO data', (0,)), | |
117 | ('miso-bits', 'MISO bits', (2,)), | |
118 | ('mosi-data', 'MOSI data', (1,)), | |
119 | ('mosi-bits', 'MOSI bits', (3,)), | |
120 | ('other', 'Other', (4,)), | |
121 | ) | |
122 | binary = ( | |
123 | ('miso', 'MISO'), | |
124 | ('mosi', 'MOSI'), | |
125 | ) | |
126 | ||
127 | def __init__(self): | |
128 | self.samplerate = None | |
129 | self.oldclk = 1 | |
130 | self.bitcount = 0 | |
131 | self.misodata = self.mosidata = 0 | |
132 | self.misobits = [] | |
133 | self.mosibits = [] | |
134 | self.misobytes = [] | |
135 | self.mosibytes = [] | |
136 | self.ss_block = -1 | |
137 | self.samplenum = -1 | |
138 | self.ss_transfer = -1 | |
139 | self.cs_was_deasserted = False | |
140 | self.oldcs = None | |
141 | self.oldpins = None | |
142 | self.have_cs = self.have_miso = self.have_mosi = None | |
143 | self.no_cs_notification = False | |
144 | ||
145 | def metadata(self, key, value): | |
146 | if key == srd.SRD_CONF_SAMPLERATE: | |
147 | self.samplerate = value | |
148 | ||
149 | def start(self): | |
150 | self.out_python = self.register(srd.OUTPUT_PYTHON) | |
151 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
152 | self.out_binary = self.register(srd.OUTPUT_BINARY) | |
153 | self.out_bitrate = self.register(srd.OUTPUT_META, | |
154 | meta=(int, 'Bitrate', 'Bitrate during transfers')) | |
155 | self.bw = (self.options['wordsize'] + 7) // 8 | |
156 | ||
157 | def putw(self, data): | |
158 | self.put(self.ss_block, self.samplenum, self.out_ann, data) | |
159 | ||
160 | def putdata(self): | |
161 | # Pass MISO and MOSI bits and then data to the next PD up the stack. | |
162 | so = self.misodata if self.have_miso else None | |
163 | si = self.mosidata if self.have_mosi else None | |
164 | so_bits = self.misobits if self.have_miso else None | |
165 | si_bits = self.mosibits if self.have_mosi else None | |
166 | ||
167 | if self.have_miso: | |
168 | ss, es = self.misobits[-1][1], self.misobits[0][2] | |
169 | bdata = so.to_bytes(self.bw, byteorder='big') | |
170 | self.put(ss, es, self.out_binary, [0, bdata]) | |
171 | if self.have_mosi: | |
172 | ss, es = self.mosibits[-1][1], self.mosibits[0][2] | |
173 | bdata = si.to_bytes(self.bw, byteorder='big') | |
174 | self.put(ss, es, self.out_binary, [1, bdata]) | |
175 | ||
176 | self.put(ss, es, self.out_python, ['BITS', si_bits, so_bits]) | |
177 | self.put(ss, es, self.out_python, ['DATA', si, so]) | |
178 | ||
179 | if self.have_miso: | |
180 | self.misobytes.append(Data(ss=ss, es=es, val=so)) | |
181 | if self.have_mosi: | |
182 | self.mosibytes.append(Data(ss=ss, es=es, val=si)) | |
183 | ||
184 | # Bit annotations. | |
185 | if self.have_miso: | |
186 | for bit in self.misobits: | |
187 | self.put(bit[1], bit[2], self.out_ann, [2, ['%d' % bit[0]]]) | |
188 | if self.have_mosi: | |
189 | for bit in self.mosibits: | |
190 | self.put(bit[1], bit[2], self.out_ann, [3, ['%d' % bit[0]]]) | |
191 | ||
192 | # Dataword annotations. | |
193 | if self.have_miso: | |
194 | self.put(ss, es, self.out_ann, [0, ['%02X' % self.misodata]]) | |
195 | if self.have_mosi: | |
196 | self.put(ss, es, self.out_ann, [1, ['%02X' % self.mosidata]]) | |
197 | ||
198 | def reset_decoder_state(self): | |
199 | self.misodata = 0 if self.have_miso else None | |
200 | self.mosidata = 0 if self.have_mosi else None | |
201 | self.misobits = [] if self.have_miso else None | |
202 | self.mosibits = [] if self.have_mosi else None | |
203 | self.bitcount = 0 | |
204 | ||
205 | def cs_asserted(self, cs): | |
206 | active_low = (self.options['cs_polarity'] == 'active-low') | |
207 | return (cs == 0) if active_low else (cs == 1) | |
208 | ||
209 | def handle_bit(self, miso, mosi, clk, cs): | |
210 | # If this is the first bit of a dataword, save its sample number. | |
211 | if self.bitcount == 0: | |
212 | self.ss_block = self.samplenum | |
213 | self.cs_was_deasserted = \ | |
214 | not self.cs_asserted(cs) if self.have_cs else False | |
215 | ||
216 | ws = self.options['wordsize'] | |
217 | ||
218 | # Receive MISO bit into our shift register. | |
219 | if self.have_miso: | |
220 | if self.options['bitorder'] == 'msb-first': | |
221 | self.misodata |= miso << (ws - 1 - self.bitcount) | |
222 | else: | |
223 | self.misodata |= miso << self.bitcount | |
224 | ||
225 | # Receive MOSI bit into our shift register. | |
226 | if self.have_mosi: | |
227 | if self.options['bitorder'] == 'msb-first': | |
228 | self.mosidata |= mosi << (ws - 1 - self.bitcount) | |
229 | else: | |
230 | self.mosidata |= mosi << self.bitcount | |
231 | ||
232 | # Guesstimate the endsample for this bit (can be overridden below). | |
233 | es = self.samplenum | |
234 | if self.bitcount > 0: | |
235 | if self.have_miso: | |
236 | es += self.samplenum - self.misobits[0][1] | |
237 | elif self.have_mosi: | |
238 | es += self.samplenum - self.mosibits[0][1] | |
239 | ||
240 | if self.have_miso: | |
241 | self.misobits.insert(0, [miso, self.samplenum, es]) | |
242 | if self.have_mosi: | |
243 | self.mosibits.insert(0, [mosi, self.samplenum, es]) | |
244 | ||
245 | if self.bitcount > 0 and self.have_miso: | |
246 | self.misobits[1][2] = self.samplenum | |
247 | if self.bitcount > 0 and self.have_mosi: | |
248 | self.mosibits[1][2] = self.samplenum | |
249 | ||
250 | self.bitcount += 1 | |
251 | ||
252 | # Continue to receive if not enough bits were received, yet. | |
253 | if self.bitcount != ws: | |
254 | return | |
255 | ||
256 | self.putdata() | |
257 | ||
258 | # Meta bitrate. | |
259 | elapsed = 1 / float(self.samplerate) | |
260 | elapsed *= (self.samplenum - self.ss_block + 1) | |
261 | bitrate = int(1 / elapsed * self.options['wordsize']) | |
262 | self.put(self.ss_block, self.samplenum, self.out_bitrate, bitrate) | |
263 | ||
264 | if self.have_cs and self.cs_was_deasserted: | |
265 | self.putw([4, ['CS# was deasserted during this data word!']]) | |
266 | ||
267 | self.reset_decoder_state() | |
268 | ||
269 | def find_clk_edge(self, miso, mosi, clk, cs): | |
270 | if self.have_cs and self.oldcs != cs: | |
271 | # Send all CS# pin value changes. | |
272 | self.put(self.samplenum, self.samplenum, self.out_python, | |
273 | ['CS-CHANGE', self.oldcs, cs]) | |
274 | self.oldcs = cs | |
275 | ||
276 | if self.cs_asserted(cs): | |
277 | self.ss_transfer = self.samplenum | |
278 | self.misobytes = [] | |
279 | self.mosibytes = [] | |
280 | else: | |
281 | self.put(self.ss_transfer, self.samplenum, self.out_python, | |
282 | ['TRANSFER', self.mosibytes, self.misobytes]) | |
283 | ||
284 | # Reset decoder state when CS# changes (and the CS# pin is used). | |
285 | self.reset_decoder_state() | |
286 | ||
287 | # We only care about samples if CS# is asserted. | |
288 | if self.have_cs and not self.cs_asserted(cs): | |
289 | return | |
290 | ||
291 | # Ignore sample if the clock pin hasn't changed. | |
292 | if clk == self.oldclk: | |
293 | return | |
294 | ||
295 | self.oldclk = clk | |
296 | ||
297 | # Sample data on rising/falling clock edge (depends on mode). | |
298 | mode = spi_mode[self.options['cpol'], self.options['cpha']] | |
299 | if mode == 0 and clk == 0: # Sample on rising clock edge | |
300 | return | |
301 | elif mode == 1 and clk == 1: # Sample on falling clock edge | |
302 | return | |
303 | elif mode == 2 and clk == 1: # Sample on falling clock edge | |
304 | return | |
305 | elif mode == 3 and clk == 0: # Sample on rising clock edge | |
306 | return | |
307 | ||
308 | # Found the correct clock edge, now get the SPI bit(s). | |
309 | self.handle_bit(miso, mosi, clk, cs) | |
310 | ||
311 | def decode(self, ss, es, data): | |
312 | if not self.samplerate: | |
313 | raise SamplerateError('Cannot decode without samplerate.') | |
314 | # Either MISO or MOSI can be omitted (but not both). CS# is optional. | |
315 | for (self.samplenum, pins) in data: | |
316 | ||
317 | # Ignore identical samples early on (for performance reasons). | |
318 | if self.oldpins == pins: | |
319 | continue | |
320 | self.oldpins, (clk, miso, mosi, cs) = pins, pins | |
321 | self.have_miso = (miso in (0, 1)) | |
322 | self.have_mosi = (mosi in (0, 1)) | |
323 | self.have_cs = (cs in (0, 1)) | |
324 | ||
325 | # Either MISO or MOSI (but not both) can be omitted. | |
326 | if not (self.have_miso or self.have_mosi): | |
327 | raise ChannelError('Either MISO or MOSI (or both) pins required.') | |
328 | ||
329 | # Tell stacked decoders that we don't have a CS# signal. | |
330 | if not self.no_cs_notification and not self.have_cs: | |
331 | self.put(0, 0, self.out_python, ['CS-CHANGE', None, None]) | |
332 | self.no_cs_notification = True | |
333 | ||
334 | self.find_clk_edge(miso, mosi, clk, cs) |